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dec, 2010 v0.18p F71808A F71808A smart lpc io with cir & power saving function release date: dec, 2010 version: v0.18p
dec, 2010 v0.18p F71808A F71808A datasheet revision history version date page revision history v0.10p 2010/2 - preliminary version v0.11p 2010/3 - add application ci rcuit and register description v0.12p 2010/4 7 11-15 16 update gpio description update pin assignment update strapping setting v0.13p 2010/5 106 42-110 15 39, 40 12, 14 1. add application circuits 2. update register 3. modify pin21 to od pin 4. add cir and cpt function descriptions 5. gpio 05, 30, 31 support scan code v0.14p 2010/5 116 15 9, 12, 14,15 39 1. update reference circuit 2. modify pin17 description 3. add sus_ack# and sus_warn# multi function on pin 19, 45, 49 4. add scan code function description v0.15p 2010/6 9, 15, 16 12, 14 12, 17 12-16 46 48, 49 49, 50 50, 51 53 54 58 74 94 100 102 112 117-125 10 1. remove sus_ack# (pin 19), add wdtrst# (pin 23) 2. rename sus_warn2# and sus_ack2# (pin 45, 49) 3. correct strap_pwok default setting 4. update pin type 5. update ldn register ? index 07h 6. update multi-function select register 0 ? index 28h 7. update multi-function select register 1 ? index 29h 8. update multi-function select register 2 ? index 2ah 9. update multi-function select register 3 ? index 2bh 10. update multi-function select register 4 ? index 2ch 11. update rs485 enable register ? index f0h 12. update fan temperature adjust select register ? index 96h 13. update gpio 23 description 14. update watchdog timer configuration register 2 ? index 06h 15. update eup enable register ? index e0h 16. update intel dsw delay select register ? index fch 17. update reference circuits 18. correct pin type v0.16p 2010/8 93 13, 15 96 96, 97 91 91, 92 92 14, 36-38 110 53 55, 56 12-15 1. correct typo 2. update pin description for gpio05, 30 and 31 3. update gpio2 input detection select register ? index d5h 4. update gpio2 event stat us register ? index d6h 5. update event pme enable register ? index c4h 6. add gpio3 input detection select register ? index c5h 7. add gpio3 event status register ? index c6h 8. correct ?s3_gate? name 9. correct power sequence control register ? index f7h bit 1 name 10. update multi-function select register 2 ? index 2ah 11. update multi-function select register 4 ? index 2ch 12. correct pwr name vcc to 3vcc v0.17p 2010/9 52 1. update multi-functi on select register 2 ? index 2ah
dec, 2010 v0.18p F71808A 15 2. correct pwok pin type v0.18p 2010/12 89 50 1. add auto swap register ? index feh (powered by vbat) bit 3 2. update multi-function select register 1 ? index 29h bit 5 description please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. life support applications these products are not designed for use in life support app liances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. customers using or selling these products for use in such applications do so at their own risk and agr ee to fully indemnify fintek for any damages resulting from such improper use or sales.
dec, 2010 v0.18p F71808A table of content 1. general descrip tion ......................................................................................................... ..... 6 2. featur e li st ................................................................................................................ ........... 6 3. key spec ification........................................................................................................... ........ 8 4. block diagram............................................................................................................... ........ 9 5. pin conf iguration ........................................................................................................... ..... 10 6. pin de scription............................................................................................................. ....... 11 6.1 powe r pin.................................................................................................................. 11 6.2 lpc inte rface ............................................................................................................ 12 6.3 uart fu nction .......................................................................................................... 12 6.4 hardware monitor ...................................................................................................... 13 6.5 acpi func tion pins ................................................................................................... 14 6.6 kbc func tion ............................................................................................................ 15 6.7 others ..................................................................................................................... .. 16 7. function descrip tion ........................................................................................................ ... 18 7.1 power on strappi ng option ....................................................................................... 18 7.2 keyboard c ontroller .................................................................................................. 18 7.3 hardware monitor ...................................................................................................... 21 7.4 acpi f unction ........................................................................................................... 34 7.5 amd tsi and intel pec i 3.0 func tion.................................................................... 39 7.6 power saving controll er ........................................................................................... 40 7.7 scan code f unction .................................................................................................. 40 7.8 cir f unction ............................................................................................................. 41 7.9 intel cougar poin t timing (c pt) ............................................................................... 42 8. register descrip tion........................................................................................................ .... 43 8.1 global control register s ........................................................................................... 47 8.2 uart register s (ldn 0x01 ) ..................................................................................... 57 8.3 hardware monitor r egister (ldn 0x04) .................................................................... 58 8.4 kbc register s (ldn 0x 05) ....................................................................................... 88 8.5 gpio registers (ldn 0x06 )...................................................................................... 89 8.6 wdt register s (ldn 0x 07)..................................................................................... 101 8.7 cir register s (ldn 0x 08) ...................................................................................... 102 8.8 pme, acpi, power saving registers (ldn 0x0a) .................................................. 104 9. electrical c haracteri stics.................................................................................................. .114 9.1 absolute maxi mum rati ngs .................................................................................... 114
dec, 2010 v0.18p F71808A 9.2 dc characte ristics .................................................................................................. 114 10.ordering in formation........................................................................................................ 116 11.package dim ensions ....................................................................................................... 117 12.applicati on circu its ........................................................................................................ .. 118
dec, 2010 v0.18p 6 F71808A 1. general description the F71808A which is the featured io chip for pc system equippes one uart port, hardware keyboard controller, hardware monitor, acpi manag ement function, cir with rc6 and smk qp protocols supported and 27 gpio pins. the F71808A integrated with hardware monitor, 6 sets of voltage sensor, 3 sets of creative auto-controlling fans and temperature sensor pins for the accurate dual current type temperature measurement for cpu thermal diode or external for temperature sensing. besides, hwm also integrated amd tsi interface and intel peci/ibex smbus interfaces for new platform tem perature reading. F71808A also fully supports peci 3.0. for amd platform, the f 71808a provides the power sequence controller function which is selected by pin power on strapping. the F71808A provides flexible features for multi-di rectional application. for instance, provides gpio pins which can be programmed by register setting, accurate current mode h/w monitor will be worth in measurement of temperature, prov ides 3 modes fan speed control mechanism included auto-linear, auto-stage and manual mode for users? selection. a power saving function which is in order to save t he current consumption when the system is in the soft off state is also integrated a power saving function. the power saving function supports that system boot-on not only by pressing the power button but also by t he wake-up event. when the system enters the s4/s5 state, F71808A can cut off the vsb power rail which supp lies power source to the devices li ke the lan chip, the chipset, the sio, the audio codec, dram, and etc. the pc system c an be simulated to g3-like state when system enters the s4/s 5 states. at the g3-like state, the f7 1808a consumes the 5vsb power rail only. the integrated two control pins are utilized to turn on or off vsb power rail in the g3-like status. the turned on vsb rail is supplied to a wake up device to fulfil a low power consumpt ion system which supports a wake up function. the F71808A is powered by 3.3v and 5vsb volt age, with the lpc interface in 64-tqfp green package. 2. feature list general functions ? comply with lpc spec. 1.1 ? support dpm (device power management), acpi ? support amd power sequence controller ? provides one uart, hardware kbc ? h/w monitor functions ? watch dog timer function ? led blink funciton ? support amd tsi interface
dec, 2010 v0.18p 7 F71808A ? intel peci 3.0 and ibex smbus interface ? 24/48 mhz clock input ? packaged in 64-tqfp and powered by 3.3vcc ? support cir with rc6 and smk qp protocols ? support intel cougar point timing ? beep function ? 27 gpio pins uart ? high-speed 16c550 compatible uart with 16-byte fifos ? fully programmable serial-interface characteris ? baud rate up to 115.2k keyboard controller ? lpc interface support serial interrupt channel 1, 12. ? two 16bit programmable address fully decoder, default 0x60 and 0x64. ? support two ps/2 interface, one for ps/2 mouse and the other for keyboard. ? keyboard?s scan code support set1, set2. ? programmable compatibility with the 8042. ? support both interrupt and polling modes. ? hardware gate a20 and hardware keyboard reset. hardware monitor functions ? 2 dual current type ( 3 ) thermal inputs for cpu thermal diode and 2n3906 transistors ? temperature range -40 ~127 ? integrate amd tsi interface ? integrate peci 3.0 spec. ? integrate ibex smbus interface ? 6 sets voltage monitoring (3 external and 3 internal powers) ? 3 fan speed monitoring inputs ? 1 pwm fan (cpu) and 2 pwm/dc fan outputs (support 3 wire and 4 wire fans) ? support 2 sets auto fan control and 1 set manual fan control. ? auto stage mode ( 4-limit and 5-stage)/auto linear mode/manual mode ? issue pme# and ovt# hardware signals output ? watchdog comparison of all monitored values watch dog timer ? time resolution minute/second by option ? maximum 256 minutes or 256 seconds ? output signal from wdtrst# pin
dec, 2010 v0.18p 8 F71808A gpio ? gpio 00 and gpio 01 can control the duty of pwm pin ? gpio 20-26 support event input for wakeup function ? gpio22-25 supports high/low/pulse/level mode option ? gpio22-25 supports interr upt event by pme/serirq ? 27 gpio pins for flexible application ? gpio05, gpio 30 and gpio 31 support scan code support amd power sequence controller power saving controller ? acpi timing and power control ? wake-up supported package ? 64-pin tqfp green package 3. key specification supply voltage 4.5v to 5.5v average operating supply current 8 ma typ.
dec, 2010 v0.18p 9 F71808A 4. block diagram cpu chipset (nb+sb) usb ide gpio com led temperature v olta g e fan super h/w monitor + i/o F71808A a cpi amd seq. ac?97 kbc amdtsi a peci 3.0 ibex smbus wdt power saving cir
dec, 2010 v0.18p 10 F71808A 5. pin configuration figure1. F71808A pin configuration
dec, 2010 v0.18p 11 F71808A 6. pin description i/o 12t i/o 12ts5v i/o 16ts - ttl level bi-directional pin with 12 ma source-sink cap ability. - ttl level bi-directional pin with schmitt trigger, 12 ma source-sink capability and 5v tolerance. - ttl level bi-directional pin with schmitt trigger, 16 ma source-sink capability. i/ood 8ts5v i/ood 12ts5v i/ood 16ts5v - ttl level bi-directional pin with schmitt trigger, open-drain output with 8 ma sink capability, 5v tolerance. - ttl level bi-directional pin with schmitt trigger, can select to od or out by register, with 12 ma source-sink capability and and 5v tolerance - ttl level bi-directional pin with schmitt trigger, can select to od or out by register, with 16 ma source-sink capability and and 5v tolerance i/od 12ts5v i/od 16ts5v - ttl level bi-directional pin with schmitt trigger, open-drain output with 12 ma sink capability, 5v tolerance. - ttl level bi-directional pin with schmitt trigger, open-drain output with 16 ma sink capability, 5v tolerance. i lv /o d8-s1 - low level bi-directional pin (vih ? 0.9v, vil ? 0.6v.). output with 8ma drive and 1ma sink capability. o 8-u47-5v o 12 o 12-5v o 16-5v o 20 o 24 - output pin with 8 ma source-sink cap ability, pull-up 47k ohms, 5v tolerance. - output pin with 12 ma source-sink capability. - output pin with 12 ma source-s ink capability, 5v tolerance. - output pin with 16 ma source-s ink capability, 5v tolerance. - output pin with 20 ma source-sink capability. - output pin with 24 ma source-sink capability. ood 12-5v ood 16-5v - od or out selected by register with 12 ma sink capability, 5v tolerance. - od or out selected by register with 16 ma sink capability, 5v tolerance. aout - output pin(analog). od 12 od 12-5v od 16-u10-5v - open-drain output pin with 12 ma sink capability. - open-drain output pin with 12 ma sink capability, 5v tolerance. - open-drain output pin with 16 ma sink ca pability, pull-up 10k ohms, 5v tolerance. in t5v in ts in ts-lv - ttl level input pin,5v tolerance. - ttl level input pin and schmitt trigger. - ttl low level input pin (vih ? 0.9v, vil ? 0.6v.) in ts5v - ttl level input pin with schmitt trigger, 5v tolerance. ain - input pin(analog). aout - output pin(analog). p - power. 6.1 power pin pin no. pin name type description 1 3vcc p power supply voltage input with 3.3v 11 gnd p digital gnd 25 i_vsb3v p 3.3v internal standby power regulates from 5vsb, couple this pin with capacitor (0.1u) to ground for inter capacitance compensation. besides, this pin can be an output pin to provide little current for battery application when system enter s erp (g3? like) state. (detail pleaser refer application circuit) 37 vbat p battery voltage input 38 5vsb (5va) p 5v stand by power input. nomally the 5v stand by power source is from atx power directly.
dec, 2010 v0.18p 12 F71808A 39 agnd(d-) p analog gnd 48 3vsb p analog stand-by power supply voltage input 3.3v 6.2 lpc interface pin no. pin name type pwr description 2 lreset# in ts 3vcc reset signal. it can connect to pcirst# signal on the host. 3 serirq i/o 12t 3vcc serial irq input/output. internal pull high 47k ohms. 4 lframe# in ts 3vcc indicates start of a new cycle or termination of a broken cycle. internal pull high 47k ohms. 8-5 lad[3:0] i/o 16ts 3vcc these signal lines communic ate address, control, and data information over the lpc bus between a host and a peripheral. internal pull high 47k ohms. 9 pciclk in ts 3vcc 33mhz pci clock input. 10 clkin in ts 3vcc system clock input. according to the input frequency 24/48mhz. 6.3 uart function pin no. pin name type pwr description gpio00 i/ood 12ts5v general purpose io. gpio function selected by register setting. gpio00/gpio01 can be selected to control pwm duty (220hz) of pwm pin. sda i/od 12ts5v smbus interface data pin. 53 dcd# in ts5v 3vcc data carrier detect. an active low signal indicates the modem or data set has detected a data carrier. gpio01 i/ood 12ts5v general purpose io. gpio function selected by register setting. gpio00/gpio01 can be selected to control pwm duty (220hz) of pwm pin. ovt# od 12-5v over temperature signal output. ovt# function selected by register setting. ri# in ts5v ring indicator. an active low signal indicates that a ring signal is being received from the modem or data set. 54 cirwb# in ts5v 3vcc cir wide-band receiver input (for learning use) gpio02 i/ood 12ts5v general purpose io. gpio function selected by register setting. cir_led od 12-5v led for cir to indicate receiver is receiving data. 55 cts# in ts5v 3vcc clear to send is the modem control input. gpio03 i/ood 16ts5v general purpose io. gpio function selected by register setting. cirtx o 20 cir transmitter to transmit data. 56 dtr# o 16-5v 3vcc uart data terminal ready. an active low signal informs the modem or data set that controller is ready to communicate.
dec, 2010 v0.18p 13 F71808A gpio04 i/ood 12ts5v general purpose io. gpio function selected by register setting. pwm ood 12-5v aout pwm or voltage output pin. the pwm output frequency can be selected from 220hz to 23.5khz or selected voltage output from 0v to 3.3v by register setting. it can support manual fan control or backlight control application. rts# o 12-5v uart request to send. an active low signal informs the modem or data set that the controller is ready to send data. 57 strap_pwok in t5v 3vcc strapping pin for amd and intel pwok. 1 default pwok (pin 35) for amd 0 pwok (pin 35) for intel gpio05 i/ood 12ts5v general purpose io. gpio function selected by register setting. add mute function (support scan code setting). low active. beep od 12 beep pin. 58 dsr# in ts5v 3vcc data set ready. an active low signal indicates the modem or data set is ready to establish a communication link and transfer data to the uart. gpio06 i/ood 8ts5v general purpose io. gpio function selected by register setting. sout o 8-u47,5v uart serial output. used to transmit serial data out to the communication link. internal 47k ohms pulled high and disable after power on strapping. 59 strap4e_2e in t5v 3vcc power on strapping: (default internal pull hight to 4e) 1 configuration register:4e (default) 0 configuration register:2e gpio07 i/ood 12ts5v general purpose io. gpio function selected by register setting. cirwb# in ts5v cir wide-band receiver input (for learning use) 60 sin in ts5v 3vcc serial input. used to receive serial data through the communication link. 6.4 hardware monitor pin no. pin name type pwr description 40 d2+ ain 3vsb thermal diode/transistor temperature sensor input2. 41 d1+ ain 3vsb thermal diode/transistor temperature sensor input1. this pin is for cpu use. 42 vref aout 3vsb voltage sensor output. power down by vcc. sus_warn2# in ts5v this pin asserts low when the pch is planning to enter the dsw power state. it can detect 5vdual level with delay setting supported. should set index 2ch bit 7 to 1 for using this pin along with pin 49 for dsw function. 45 vin3(vdimm) ain 3vsb voltage input 3. voltage input for vdimm dual str
dec, 2010 v0.18p 14 F71808A (2.5v/1.8v). 0.9v power ok. 46 vin2(vldt) ain 3vsb voltage input 2. voltage input for vldt (1.2v). 0.9v power ok. 47 vin1(vcore) ain 3vsb voltage input for vcore. 0.6v power ok. 61 fanin1 in ts5v 3vcc fan 1 for cpu fan tachometer input. 62 fanctl1 od 12-5v 3vcc fan 1 control output for cpu fan. this pin provides only pwm duty-cycle output. fanin2 in ts5v fan 2 tachometer input. 63 gpio35 i/ood 12ts5v 3vcc general purpose io. gpio function selected by register setting. fanctl2 ood 12-5v aout fan 2 control output. this pin provides pwm duty-cycle output or a voltage output. pull up 4.7k to vcc to for pwm mode option. 64 gpio34 i/ood 12ts5v 3vcc general purpose io. gpio function selected by register setting. peci i lv /o d8-s1 intel peci hardware monitor interface. sda i/od 12ts5v smbus interface data pin. 51 gpio32 i/ood 12ts5v 3vcc general purpose io. gpio function selected by register setting. gpio33 i/ood 12ts5v general purpose io. gpio function selected by register setting. 52 scl i/od 12ts5v 3vcc smbus interface clock pin. 6.5 acpi function pins pin no. pin name type pwr description 24 s 3 _gate o 12 i_vsb3v switch 3vsb power to me mory when in s3 state in s0# ( low level in s3# ( drive high in s5# ( default is low level, and can be programmed to drive high slp_sus# in st-lv for intel cpt dsw function. connect to pch slp_sus pin. gpio26 i/ood 12ts5v general purpose io. gpio function selected by register setting. wdtrst# od 12-5v watch dog timer signal output. wdtrst# function selected by register setting. 27 rstcon# in ts5v i_vsb3v connect to reset button. internal with de-bounce circuit which is at least 50ms. pull-high 10kohm to vsb3v internally. 28 pcirst1# od 12-5v i_vsb3v it is an output buffer of lreset#. this pin supports software reset by program. 29 pcirst2# o 24 i_vsb3v it is an output buffer of lreset#. this pin supports software reset by program. 30 s5# in ts5v i_vsb3v s5# signal input.
dec, 2010 v0.18p 15 F71808A psin# in ts5v main power switch button input. 31 gpio27 i/ood 12ts5v i_vsb3v general purpose io. support high/low/pulse/level selection. gpio function selected by register setting. psout# od 12-5v panel switch output. this pin is low active and pulse output. it is power on request output#. 32 gpio14 i/ood 12ts5v i_vsb3v general purpose io. gpio function selected by register setting. 33 s3# in ts5v i_vsb3v s3# input is main power on-off switch input. 34 pson# od 12-5v i_vsb3v power supply on-off control output. connect to atx power supply ps_on# signal. 35 pwok i/od 12 vbat pwrok function, it is power good signal of vcc, which is delayed 400ms (default) as vcc arrives at 2.8v. 36 rsmrst# od 12 vbat resume reset# function, it is power good signal of vsb, which is delayed 66ms as vsb arrives at 2.8v. sus_ack2# ood 16-5v this pin must wait sus_warn2# signal for entering dsw power state. should set index 2ch bit 7 to 1 for using this pin along with pin 45 for dsw function. vcore_en od 12-5v active high. the function of this pin is to enable the pwm for cpu vcore. the external pull high resistor is required. 49 gpio30 i/ood 12ts5v 3vsb general purpose io. gpio function selected by register setting. it can control the system volume from lpc interface (support scan code setting). low active. vldt_en od 12-5v active high. the function of this pin is to enable the vldt voltage. the external pull high resistor is required. gpio31 i/ood 12ts5v general purpose io. gpio function selected by register setting. it can control the system volume from lpc interface (support scan code setting). low active. 50 sda i/od 12ts5v 3vsb smbus interface data pin. 6.6 kbc function pin no. pin name type pwr description 12 kbrst# od 16-u10,5v 3vcc keyboard reset. this pin is high after system reset. internal pull high 3.3v with 10k ohms. (kbc p20) 13 ga20 od 16-u10,5v 3vcc gate a20 output. this pin is high after system reset. internal pull high 3.3v with 10k ohms. (kbc p21) kdat i/od 16ts5v keyboard data. gpio10 i/ood 16ts5v general purpose io. gpio function selected by register setting. 14 fanin3 in ts5v i_vsb3v fan 3 tachometer input. selected by register setting. kclk i/od 16ts5v keyboard clock. gpio11 i/ood 16ts5v general purpose io. gpio function selected by register setting. 15 ovt# od 12-5v i_vsb3v over temperature signal output. ovt# function selected by register setting. 16 sus_ack# ood 16-5v this pin must wait suswarn# signal for entering
dec, 2010 v0.18p 16 F71808A dsw power state. mdat i/od 16ts5v ps2 mouse data. use with pin 17 for dsw gpio12 i/ood 16ts5v i_vsb3v general purpose io. gpio function selected by register setting. sus_warn# in ts5v this pin asserts low when the pch is planning to enter the dsw power state. it can detect 5vdual level with delay setting supported. use with pin 16 for dsw. mclk i/od 16ts5v ps2 mouse clock. gpio13 i/ood 16ts5v general purpose io. gpio function selected by register setting. 17 cirwb# in ts5v i_vsb3v cir wide-band receiver input. (for learning use) 6.7 others pin no. pin name type pwr description gpio20 i/ood 12ts5v general purpose io. gpio function selected by register setting. 18 pme# od 12-5v i_vsb3v generated pme event. it supports the pci pme# nterface. this signal allows the peripheral to request the system to wake up from the s3 state. gpio21 i/ood 12ts5v general purpose io. gpio function selected by register setting. fanin3 in ts5v fan 3 tachometer input. selected by register setting. 19 ovt# od 12-5v i_vsb3v over temperature signal output. ovt# function selected by register setting. erp_ctrl1# od 12-5v standby power rail control pin 1. this pin controls an external pmos to turn on or off the standby power rail. in the s5 state, the default is set to 1 to cut off the standby power rail. pwm ood 12-5v aout pwm or voltage output pin. the pwm output frequency can be selected from 220hz to 23.5khz or selected voltage output from 0v to 3.3v by register setting. it can support manual fan control or backlight control application. 20 gpio22 i/ood 12ts5v i_vsb3v general purpose io. support high/low/pulse/level selection. dpwrok od 12-5v resume reset# function, it is power good signal of vsb, which is delayed 66ms as vsb arrives at 4.4v. couple this pin to pch when system supports intel dsw state function. gpio23 od 12-5v general purpose pin. support high/low/pulse/level selection. wdtrst# od 12-5v watch dog timer signal output. wdtrst# function selected by register setting. 21 fanin3 in ts5v i_vsb3v fan 3 tachometer input. selected by register setting. 22 gpio24 i/ood 12ts5v i_vsb3v general purpose pin. support high/low/pulse/level selection.
dec, 2010 v0.18p 17 F71808A ledvsb od 12-5v power led for vsb. blin k frequency selection. ledvsb function selected by register setting. gpio25 i/ood 12ts5v general purpose pin. support high/low/pulse/level selection. ledvcc od 12-5v power led for vcc. blink frequency selection. ledvcc function selected by register setting. 23 wdtrst# od 12-5v i_vsb3v watch dog timer signal output. wdtrst# function selected by register setting. 26 erp_ctrl0# od 12 i_vsb3v standby power rail control pin 0. this pin controls an external pmos to turn on or off the standby power rail. in the s5 state, the default is set to 1 to cut off th e standby power rail. 43 cirrx# in ts5v i_vsb3v cir long-range receiver input 44 copen# in ts5v vbat case open detection #. this pin is connected to a specially designed low power cmos flip-flop back by the battery for case open state preservation during power loss.
dec, 2010 v0.18p 18 F71808A 7. function description 7.1 power on strapping option the F71808A provides one pin for power on hardware strapping to select the function. there is a form to describe how to set the function you want. table1. power on trap configuration pin no. symbol value description 1 pwok (pin 35) for amd (default) 57 strap_pwok 0 pwok (pin 35) for intel 1 configuration register i/o port is 4e. (default) 59 strap4e_2e 0 configuration register i/o port is 2e. 7.2 keyboard controller the kbc circuit provides the functions included a keyboard and/or a ps/2 mouse, and can be used with ibm ? -compatible personal computers or ps/2-based sy stems. the controller receives serial data from the keyboard or ps/2 mouse, checks the parity of the data, and presents the data to the system as a byte of data in its output buffer. the controller will assert an interrupt to the system when data are placed in its output buffer. output buffer the output buffer is an 8-bit read-only register at i/o address 60h. the keyboard controller uses the output buffer to send the scan code received from t he keyboard and data bytes required by commands to the system. input buffer the input buffer is an 8-bit write-only register at i/o address 60h or 64h. writing to address 60h sets a flag to indicate a data write; writing to address 64h sets a flag to indicate a command write. data written to i/o address 60h is sent to keyboard th rough the controller's input buffer only if the input buffer full bit in the status register is ?0?. status register
dec, 2010 v0.18p 19 F71808A the status register is an 8-bit read-only register at i/o address 64h, that holds information about the status of the keyboard controller and interface. it may be read at any time. bit bit function description 0 output buffer full 0: output buffer empty 1: output buffer full 1 input buffer full 0: input buffer empty 1: input buffer full 2 system flag this bit may be set to 0 or 1 by writing to the system flag bit in the command byte of the keyboard controller (kccb). it defaults to 0 after a power-on reset. 3 command/data 0: data byte 1: command byte 4 inhibit switch 0: keyboard is inhibited 1: keyboard is not inhibited 5 mouse output buffer 0: muse output buffer empty 1: mouse output buffer full 6 general purpose time-out 0: no time-out error 1: time-out error 7 parity error 0: odd parity 1: even parity (error) commands command fucntion 20h read command byte 60h write command byte bit description 0 enable keyboard interrupt 1 enable mouse interrupt 2 system flag 3 reserve 4 disable keyboard interface 5 disable mouse interface 6 ibm keyboard translate mode 7 reserve a7h disable auxiliary device interface a8h enable auxiliary device interface
dec, 2010 v0.18p 20 F71808A a9h auxiliary interface test 8?h00: indicate auxiliary interface is ok. 8?h01: indicate auxiliary clock is low. 8?h02: indicate auxiliary clock is high 8?h03: indicate auxiliary data is low 8?h04: indicate auxiliary data is high aah self-test returns 055h if self test succeeds abh keyboard interface test 8?h00: indicate keyboard interface is ok. 8?h01: indicate keyboard clock is low. 8?h02: indicate keyboard clock is high 8?h03: indicate keyboard data is low 8?h04: indicate keyboard data is high adh disable keyboard interface aeh enable keyboard interface c0h read input port(p1) and send data to the system c1h continuously puts the lower four bi ts of port1 into status register c2h continuously puts the upper four bi ts of port1 into status register cah read the data written by cbh command. cbh written a scratch data. this byte could be read by cah command. d0h send port2 value to the system d1h only set/reset gatea20 line based on the system data bit 1 d2h send data back to the system as if it came from keyboard d3h send data back to the system as if it came from muse d4h output next received byte of data from system to mouse feh pulse only rc(the reset line) low for 6 s if command byte is even kbc command description ps2 wakeup function the kbc supports keyboard and mouse wakeup function, keyboard wakeup function has 4 kinds of conditions, when key is pressed combinational ke y (1) ctrl +esc (2) ctrl+f1 (3) ctrl+ user defined code (4) any key (5) windows 98 wakeup up key (6) windows 98 power key (7) ctrl + alt + user defined code (8) user defined code, kbc will assert pme signal. mouse wakeup function has 2 kinds of conditions, when mouse (1) button click or (2) button click and movement, kbc will assert pme signal. those wake up conditions are cont rolled by configuration register.
dec, 2010 v0.18p 21 F71808A 7.3 hardware monitor for the 8-bit adc has the 8mv lsb, the maxi mum input voltage of the analog pin is 2.048v. therefore the voltage under 2.048v (e x: 1.5v) can be directly connec ted to these analog inputs. the voltage higher than 2.048v should be reduced by a factor with external resistors so as to obtain the input range. only 3vcc/vsb/vbat is an exception for it is main power of the F71808A. therefore 3vcc/vsb/vbat can directly connect to this chip?s power pin and need no external resistors. there are two functions in this pin with 3.3v. the first function is to supply internal analog power of the F71808A and the second function is that voltage with 3. 3v is connected to internal serial resistors to monitor the +3.3v voltage. the internal serial re sistors are two 150k ohm, so that the internal reduced voltage is half of +3.3v. there are three voltage inputs in the F71808A and the voltage divided formula is shown as follows: 2 1 2 12 r r r v vin v + = + where v +12v is the analog input voltage, for example. if we choose r1=27k, r2=5.1k, the exact input volt age for v+12v will be 1.907v, which is within the tolerance. as for application circuit, it can be refer to the figure shown as follows. vin (lower than 2.048v) 8-bit adc with 8 mv lsb voltage inputs r1 r2 vin1(max2.048v) vin(higher than 2.048v) (directly connect to the chip) 3vcc/vsb (directly connect to the chip) vin3.3 150k 150k typical thermister connection r thm 10k, 25 c r vref 10k, 1% 2n3906 typical bjt connection d+ d- figure2. hardware monitor configuration the F71808A monitors two remote temperature sens ors.these sensors can be measured from -40c to 127c. more detail, please refer register description.
dec, 2010 v0.18p 22 F71808A table2. remote-sensor transistor manufacturers manufacturer model number panasonic 2sb0709 2n3906 philips pmbt3906 table range: table3. display range is from -40c to 127c in 2?s complement format. temperature digital output -40c 1101 1000 -1c 1111 1111 1c 0000 0001 90c 0101 1010 127c 0111 1111 open 1000 0000 monitor temperature from ?thermistor? the F71808A can connect two thermistors to measure environment temperature or remote temperature. the specification of thermistor should be considered to (1) value is 3435k (2) resistor value is 10k ohm at 25c. in the figure 6-1, the ther mistor is connected by a serial resistor with 10k ohm, and then connected to vref. the temperature measurement range is 0~127c. monitor temperature from ?thermal diode? also, if the cpu, gpu or external circuits prov ide thermal diode for temperature measurement, the F71808A is capable to these situations. the build-i n reference table is for pnp 2n3906 transistor. in the figure 7-1, the transistor is dire ctly connected into temperature pins. adc noise filtering the adc is integrating type with inherently good noise rejection. micro-power operation places constraints on high-frequency noise rejection; t herefore, careful pcb board layout and suitable external filtering are required for high-accuracy remote measurement in electronically noisy environment. high frequency emi is best filtered at d+ and d- with an external 2200pf capacitor. too high capacitance may introduce errors due to the rise time of the switched cu rrent source. nearly all noise sources tested cause the adc measuremen t to be higher than the actual temperature, depending on the frequency and amplitude.
dec, 2010 v0.18p 23 F71808A monitor temperature from ?smbus device? F71808A provides smbus ?block read? compat ible pch ec smbus protocol and provides ?send/receive byte? protocol to read cpu and chipset thermal temperature information. monitor temperature from ?peci? F71808A support intel peci 3.0 interface to read temperature from peci 3.0 device. temperature hm_irq signal (hm_irq# and pme#) over temperature event will trigger hm_irq # that shown as figure. when monitored temperature exceeds the high temperature thres hold value, hm_irq# will be asserted until the temperature goes below the hy steresis temperature. t hyst t hm_irq# high figure 3 pme# interrupt for temperature is shown as figure. temperature exceeding high limit (low limit) or going below high hysteresis (low hysteresis) w ill cause an interrupt if the previous interrupt has been reset by writing ?1? all the interrupt status register. *interrupt reset when interrupt status registers are written 1 pme# t low (pulse mode) * * t high t hhys t lhys * * figure 4 hysteresis mode illustration fan speed count
dec, 2010 v0.18p 24 F71808A inputs are provided by the signals from fans equipped with tachometer outputs. the level of these signals should be set to ttl level, and maximum input voltage cannot be over 5v. if the input signals from the tachometer output s are over the 5v, the external trimming circuit should be added to reduce the voltage to obtain the input specification. determine the fan counter according to: r pm count 6 10 5 . 1 = in other words, the fan speed counter has been read from register, the fan s peed can be evaluated by the following equation. as for fan, it would be best to use 2 pulses tachometer output per round. count rpm 6 10 5 . 1 = fan speed control the F71808A provides 2 fan speed control methods: 1. dac fan control 2. pwm duty cycle dac fan control only fanctl2/fanctl3 support dac (voltage) f an control. the range of dc output is 0~3.3v, controlled by 8-bit register. 1 lsb is about 0.013v. the output dc voltage is amplified by external op circuit, thus to reach maximum fan operation voltage, 12v. the output voltage will be given as followed: 255 value register 8bit programmed 3 . 3 (v) tage output_vol = and the suggested application circuit for linear fan control would be: dc output voltage r 3.9k r10k 12v pmos r27k 1 2 3 jp1 con3 r 10k d1 1n4148 r 4.7k c 47u fanin monitor c 0.1u 3 2 1 8 4 + - lm358 dc fan control with op figure 5 dac fan control application circuit
dec, 2010 v0.18p 25 F71808A pwm duty fan control the duty cycle of pwm can be programmed by an 8-bi t register. the default duty cycle is set to 100%, that is, the default 8-bit registers is set to ffh. the expression of duty can be represented as follows. % 100 255 value register 8bit programmed (%) duty_cycle = +12v fan r1 r2 nmos pnp transistor c + - d s g figure 6 +12/5v pwm fan control application circuit fan speed control mechanism there are some modes to control fan speed and they are 1.manual mode, 2.stage auto mode 3. linear auto mode. more detail, please re fer the description of registers. each fan can be controlled by up to 7 kinds of temperature input. (1)d1+ temperature (2)d2+ temperature (3) peci temperature (4) 4 suits smbus master temperature. please refer below structure diagram.
dec, 2010 v0.18p 26 F71808A [ figure 7 relative temperature fan control manual mode for manual mode, it generally acts as software fan speed control. auto mode in auto mode, the F71808A provides automatic fan speed control related to temperature variation of cpu/gpu or the system. the F71808A can provide four temperature boundaries and five intervals, and each interval has its related fan speed count. all these values should be set by bios first. take fan1 for example, the 4 temperature b oundaries could be set from register 0xa6 to 0xa9 and the five intervals for fan speed control coul d be set from register 0xaa to 0xae. and the hysteresis setting (0 ~ 15c) could also be found in register 0x98. the manual mode and auto mode could be selected by register 0x96h. there are two kinds of auto mode: stag e auto mode and linear auto mode. the ?fan1_ interpolation_en? in register 0xafh is used for linear auto mode enable. the following examples explain the differences fo r stage auto mode and linear auto mode. stage auto mode in this mode, the fan keeps in a same speed fo r each temperature interval. and there are two types of fan speed setting: pwm duty and rpm %. a. stage auto mode (pwm duty) set the temperature limits as 70c, 60c, 50c, 40 c and the duty as 100%, 90%, 80%, 70%, 60% expect speed1 expect speed 2 fan1 fan2 d2+ t (t2) d1+ t (t1) peci ibx byte1 ibx byte3:2 ibx byte4 ibx byte5 expect speed 3 fan3
dec, 2010 v0.18p 27 F71808A figure 8 stage mode fan control illustration-2 a. once the temperature is under 40c, the lowest fan speed keeps in the 60% pwm duty. b. once the temperature is over 40c, 50cand 60 c, the fan speed will vary from 70%, 80% to 90% pwm duty and increasing with the temperature level. c. for the temperature higher than 70c, the fan speed keeps in 100% pwm duty. d. if set the hysteresis is 3c (default 4c), onc e the temperature becomes lower than 67c, the fan speed would reduce to 90% pwm duty. b. stage auto mode (rpm%) set the temperature as 70c, 60c, 50c, 40 c and the corresponding fan speed is 6,000 rpm, 5,400 rpm, 4,800 rpm, 4,200 rpm, and 3,600 rpm (assume the max fan speed is 6,000 rpm).
dec, 2010 v0.18p 28 F71808A figure 9 stage mode fan control illustration-3 a. once the temperature is lower than 40c, the lowest fan speed keeps in 3,600 rpm (60% of full speed). b. once the temperature is higher than 40c, 50c and 60c, the fan speed will vary from 4,200 rpm to 5,400 rpm and increasing with the temperature level. c. for the temperature higher than 70c, the fan speed keeps in the full speed 6,000 rpm. d. if the hysteresis is set as 3c (default 4c) , once temperature gets lower than 67c, the fan speed would reduce to 5,400 rpm. linear auto mode F71808A also supports linear auto mode. the fan speed would increase or decrease linearly with the temperature. there are also pwm duty and rpm% modes for it. a. linear auto mode (pwm duty) set the temperature as 70c, 60c, 50c and 40c and the duty is 100%, 80%, 70%, 60% and 50%.
dec, 2010 v0.18p 29 F71808A figure 10 linear mode fa n control illustration-1 a. once the temperature is lower than 40c, the lowest fan speed keeps in the 50% pwm duty b. once the temperature becomes higher than 40c , 50c and 60c, the fan speed will vary from 50% to 80% pwm duty linearly with the tempreat ure variation. the temp.-fan speed monitoring flash interval is 1sec. c. once the temperature goes over 70c, the fan speed will directly increase to 100% pwm duty (full speed). d. if set the hysteresis is 5c (default is 4c) , once the temperature becomes lower than 65c (instead of 70c), the fan speed will reduce from 100% pwm duty and decrease linearly with the temperature. b. linear auto mode (rpm%) set the temperature as 70c, 60c, 50c, 40 c and the corresponding fan speed is 6,000 rpm, 4,800 rpm, 4,200 rpm, 3,600 rpm and 3,000 rpm (assume the max fan speed is 6,000 rpm).
dec, 2010 v0.18p 30 F71808A figure 11 linear mode fa n control illustration-2 a. once the temperature is lower than 40c, the lowest fan speed keeps in 3,000 rpm (50% of full speed). b. once the temperature is over 40c,50c and 60 c, the fan speed will vary from 3,000 to 4,800 rpm almost linearly with the temperature variation because the temp.-fan speed monitoring flash interval is 1sec. c. once the temperature goes over 70c, the f an speed will directly increase to full speed 6,000 rpm. d. if the hysteresis is 5c (default is 4c), onc e the temperature becomes lower than 65c (instead of 70c), the fan speed wull reduce from full s peed and decrease linearly with the temperature.
dec, 2010 v0.18p 31 F71808A fan speed control with multi-temperature. F71808A supports multi-temperature for one fan c ontrol. this function works with linear auto mode can extend two linear slopes for one fan control. as the graph below, this machine can support more silence fan control in low temperature environment and faster fan speed in high temperature segment. more detail setting please refers to the registers.
dec, 2010 v0.18p 32 F71808A in the figure below, tfan1 is the scaled temperatur e for fan1. t1 is the real temperature for the fan1 sensor. ta is another temperature data which ca n be used for linearly scale up or scale down the fan1 speed curve. tb would be the point which star ts the temperature scaling. the slope for the temperature curve over and under tb would be ctup and ctdn. in application, we can set the ta as the 2nd sens or temperature and tb as the temperature which starts the scaling. so if the 2nd sensor temperat ure ta is higher or lower than tb, the fan1 speed would be changed with it.
dec, 2010 v0.18p 33 F71808A ex: ta = t1, tb = 60, ctu = 1, ctd = 1/4 pwmout duty-cycle operating process in both ?manual rpm? and ?temperature rp m? modes, the F71808A adjust pwmout duty-cycle according to current fan count and ex pected fan count. it will operate as follows: (1). when expected count is 0xfff, pwmout du ty-cycle will be set to 0x00 to turn off fan. (2). when expected count is 0x000, pwmout duty- cycle will be set to 0xff to turn on fan with full speed. (3). if both (1) and (2) are not true, (4). when pwmout duty-cycle decrease to min_duty( 00h), obviously the duty-cycle will decrease to 00h next, the F71808A will keep duty- cycle at 00h for 1.6 seconds. after that, the F71808A starts to compare current fan c ount and expected count in order to increase or decrease its duty-cycle. this ensures that if there is any glitch during the period, the F71808A will ignore it.
dec, 2010 v0.18p 34 F71808A start duty stop duty figure 12 fan_fault# fan_fault# will be asserted when the fan speed do esn?t meet the expected fan speed within a programmable period (default is 11 seconds) or when fan stops with respect to pwm duty-cycle which should be able to turn on the fan. there ar e two conditions may cause the fan_fault# event. (1). when pwm_duty reaches 0xff, the fan speed count can?t reach the fan expected count in time. (figure 13) fan_fault# expected fan count 11 sec ( default ) current fan count duty-cycle 100% figure 13 fan_fault# event (2). after the period of detecting fan full speed, when pwm_duty > min. duty, and fan count still in 0xfff. 7.4 acpi function the advanced configuration and power interf ace (acpi) is a system for controlling the use of power in a computer. it lets computer manufacture r and user to determine the computer?s power usage dynamically. there are three acpi states that are of primar y concern to the system designer and they are designated s0, s3 and s5. s0 is a full-power state; the computer is being actively used in this state. the other two are called sleep states and reflect differ ent power consumption when power-down. s3 is a state that the processor is powered down but the last procedural state is being stored in memory which is still active. s5 is a state that memory is off and the last procedural state of the processor has been stored to the hard disk. take s3 and s5 as comparison, si nce memory is fast, the computer can quickly come back to full-power state, the disk is slower than the memory and the computer takes longer time to come back to full-power state. however, since the memory is off, s5 draws the minimal power comparing to s0 and s3. it is anticipated that only the following state transitions may happen:
dec, 2010 v0.18p 35 F71808A s0 s3, s0 s5, s5 s0, s3 s0 and s3 s5. among them, s3 s5 is illegal transition and won?t be allowed by state machine. it is necessary to enter s0 first in order to get to s5 from s3. as for transition s5 s3 will occur only as an immediate state during state transition from s5 s0. it isn?t allowed in the normal state transition. the below diagram described the timing, the always on and always off, keep last state could be set in control register. in keep last state mode, one regist er will keep the status of before power loss. if it is power on before power loss, it will remain power on w hen power is resumed, otherwise, if it is power off before power loss, it will remain power off when power is resumed. vbat vsb rsmrst# s3# ps_on# psin# psout# vcc3v figure 14 default timing: always off vbat vsb rsmrst# s3# ps_on# psin# psout# vcc3v
dec, 2010 v0.18p 36 F71808A figure 15 optional timing: always on the F71808A offers 2 timing pins which are designed for amd platform power sequence control including vcore and vldt (default) or other timing application purposes. all the timings on/off are relative to s3#/s5# and can be programmed by the regi ster 0x0af7. as shown in the below figure, the default timings of vcore and vldt are displayed in blue lines. vddok_d400 is the pwrok delay timing from vdd3vok. the default setting is that delay 400ms, there are 100ms, 200ms, and 300ms for option. it can be set in the register 0x0af5. figure 16 amd power sequence s 3 _gate timing the s 3 _gate is used to switch the power source of the 5vdual which is combined by the 5vcc and 5vsb rails according to the acpi state to control th e power rail of the dimm especially. the timing charts of the every acpi state are mentioned in the following figures.
dec, 2010 v0.18p 37 F71808A figure 17 s 3 _gate timing: s5 ? s0 figure 18 s 3 _gate timing: s0 ? s3
dec, 2010 v0.18p 38 F71808A figure 19 s 3 _gate timing: s3 ? s0 figure 20 s 3 _gate timing: s0 ? s5
dec, 2010 v0.18p 39 F71808A pci reset and pwok signals the F71808A supports 2 output buffers for 2 reset signals. so far as the pwok issue is as the figure above. pwok is delayed 400ms (default) as vcc arrives 2.8v, and the delay timing can be programmed by regi ster (100ms ~ 400ms). an additional delay could be added to pwok (0ms, 100ms, 200ms and 400ms). def ault is 0ms. rstcon# could be programmed to be asserted via pwok. 7.5 amd tsi and intel peci 3.0 function the F71808A provides intel peci/amd tsi interfaces for new generational cpu temperature sensing. in amd tsi interface, there are si c and sid signals for temperature information reading from amd cpu. the sic signal is for clocking use, the other is for data transferring. more detail, please refer the register description. scl vddio amd cpu tsi_clk tsi_dat 300 300 sda f71808 a figure 21 amd tsi typical application in intel peci interface, the F71808A can connect to cpu directly. the F71808A can read the temperature data from cpu, than the fan control mach ine of F71808A can implement the fan to cool down cpu temperature. the application circuit is as below. more detail please refer to the register descriptions. peci F71808A cpu peci intel 100k avoid pre-bios floating figure 22 intel peci typical application delay +3.3v rstcon# lreset# pcirst1~2# pwok buffer
dec, 2010 v0.18p 40 F71808A F71808A support peci 3.0 command name peci 1.0 command name status v ping( ) ping( ) v gettemp( ) gettemp( ) v getdib( ) v rdiamsr( ) - wriamsr( ) - rdpciconfiglocal( ) not available in mobile/dt - wrpciconfiglocal( ) not available in mobile/dt - rdpciconfig( ) not available in mobile/dt - wrpciconfig( ) not available in mobile/dt v rdpkgconfig( ) v wrpkgconfig( ) 7.6 power saving controller the two pins, erp_ctrl0# and erp_ctrl1#, which control the standby power rail on/off to fulfil the purpose which decreases the power consumption when the system in the sleep state or the soft-off state. these two pins connected to the external pmoss and t he defaults are high in the sleep state in order to cut off all the standby power rails to save the power co nsumption. if the system needs to support wake-up function, the two pins can be programmable to set wh ich power rail is turned on. the programmable register is powered by battery. so, the setting is kept even the ac power is lost when the register is set. at the power saving state (fintek calls it g3-like state), the f 71808a consumes 5vsb power rail only to realize a low power consumption system. 7.7 scan code function F71808A has 3 gpio pins (gpio05, 30, 31) support scan code. these pins can not only be set to volume up/down and mute but also any function keys on keyboard. because the protocol for these 3 pins is scan code, so we don?t need a driver to connect this function to os. if the button for the gpio has been pressed continuesly over near ly 1 second, the gpio will repeatedly sending this function in an interval of 50 ms.
dec, 2010 v0.18p 41 F71808A 7.8 cir function the F71808A is compatible with microsoft windows vista and windows 7 ir receiver or transceiver emulation device which supports rc6 & qp protocol. it supports 1 ir transceiver functions for blaster application and 1 ir receiver with long range frequency and another with wide band application. in power function, the F71808A supports vista and windows 7 wakeup programming function when the pc is in the s3 state. the F71808A decode ir protocol via the same vista and windows 7 wakeup programming key. the F71808A is asserted pme or psout to wakeup pc system. where wake up programming function is reference from microsoft vista and windows 7 remote controller specification. the F71808A supports 1 ir transceiver function for blaster application and two ir receivers for long range frequency and wideband application. the wide-band receiver is necessary to support ir learning, ir-blasting and set-top box control. the long-range receiver is a receiver which has the following characteristics: 1. works at a distance of 10 meters. 2. demodulates the signal inside the receiver part 3. has a bpf which works with carriers from 32-60 khz. the wide-band receiver is a receiver part which has the following characters: 1. works at a distance of approximately 5 centimeters. 2. does not demodulate the signal inside the receiver part 3. works with carriers from 32-60 khz. (probably doesn?t have a bpf, but still has the same (or wider) range. about ir information, reference microsoft wi ndows vista / 7 ir receiver or transceiver emulation device spec.
dec, 2010 v0.18p 42 F71808A 7.9 intel cougar point timing (cpt) the F71808A supports intel cougar point chipset timing for sandy bridge. there are 4 pins for cpt control: sus_warn#, sus_ack#, slp_sus# and dpwrok. for entering intel deep sleep well (dsw) state, the pch will assert sus_warn# and turn off 5vdual. after the level of 5vdual is lower than 1.05v, F71808A will assert sus_ack# to inform pch it is ready for entering dsw. finally, pch will ramp down the internal vccsus and assert slp_sus# to F71808A. F71808A will turn off the 5vsb and 3vsb by erp_ctrl0# and enter the dsw state. to exit dsw state, pch will de-assert slp_sus#, turn on the sus rail fets and ramp up internal 1.05v vccsus. after the sus rails voltages are up, rsmrst# will be desserted and the pch will release sus_warn# so that the 5vdual will ramp up. because the dsw function is controlled by F71808A instead of controlled by pch directly, there will be more wakeup events such as lan, kb/mouse, sio ri# wake up rather than the 3 wakeup events (rtc, power button and gpio27) for intel dsw. in order to achieve lower power consumption, F71808A provides the erp_ctrl1# to turn off the v3a so that the system can enter the fintek g3? state. the block diagram below shows how the connection and control method for F71808A and pch.
dec, 2010 v0.18p 43 F71808A 8. register description the configuration register is used to control the behavior of the co rresponding devices. to configure the register, using the index port to select the index and then writing data port to alter the parameters. the default index port and data port are 0x4e and 0x4f respectively. pull down the sout pin to change the default value to 0x2e/0x2f. to enable configuration, th e entry key 0x87 must be written to the index port. to disable configuration, write exit key 0xaa to the index port. following is a example to enable configuration and disable conf iguration by using debug. -o 4e 87 -o 4e 87 (enable configuration) -o 4e aa (disable configuration) the following is a register map (total devices) gr ouped in hexadecimal addr ess order, which shows a summary of all registers and their default value. pleas e refer each device chapter if you want more detail information. global control registers ?-? reserved or tri-state global control registers register 0x[hex] register name default value msb lsb 02 software reset register - - - - - - - 0 07 logic device number register (ldn) 0 0 0 0 0 0 0 0 20 chip id register 0 0 0 1 0 0 0 0 21 chip id register 0 0 0 0 0 0 0 1 23 vendor id register 0 0 0 1 1 0 0 1 24 vendor id register 0 0 1 1 0 1 0 0 25 software power down register - - - - - - 0 - 26 clock select register 0 - - - - 0 - - 27 configuration port select register 0 0 0 0 0 0 0 1 28 multi-function select register 0 0 0 0 0 0 0 0 0 29 multi-function select register 1 1 1 0 0 0 0 0 0 2a multi-function select register 2 0 0 1 0 0 0 0 0 2b multi-function select register 3 0 1 1 1 1 1 1 1 2c multi-function select register 4 0 0 0 0 1 1 0 0
dec, 2010 v0.18p 44 F71808A 2d wakeup control register 0 0 1 0 1 0 0 0 device configuration registers ?-? reserved or tri-state uart device configuration registers (ldn 0x01) register 0x[hex] register name default value msb lsb 30 uart device enable register - - - - - - - 1 60 base address high register 0 0 0 0 0 0 1 1 61 base address low register 1 1 1 1 1 0 0 0 70 irq channel select register - - - - 0 1 0 0 f0 rs485 enable register - - 0 0 - - - - hardware monitor device configuration registers (ldn 0x04) register 0x[hex] register name default value msb lsb 30 h/w monitor device enable register - - - - - - - 1 60 base address high register 0 0 0 0 0 0 1 0 61 base address low register 1 0 0 1 0 1 0 1 70 irq channel select register - - - - 0 0 0 0 kbc device configuration registers (ldn 0x05) register 0x[hex] register name default value msb lsb 30 kbc device enable register - - - - - - - 1 60 base address high register 0 0 0 0 0 0 0 0 61 base address low register 0 1 1 0 0 0 0 0 70 kb irq channel select register - - - - 0 0 0 1 72 mouse irq channel select register - - - - 1 1 0 0 fe swap register 0 - - 0 0 0 0 1 ff user wakeup code register 0 0 1 0 1 0 0 1 gpio device configuration registers (ldn 0x06) register 0x[hex] register name default value msb lsb 70 gpirq channel select register - - - - 0 0 0 0 c0 gpio3 output enable register - - 0 0 0 0 0 0 c1 gpio3 output data register - - 1 1 1 1 1 1 c2 gpio3 pin status register - - - - - - - - c3 gpio3 drive enable register - - 0 0 0 0 0 0 c4 event smi enable register - - - 0 0 0 0 0
dec, 2010 v0.18p 45 F71808A c5 event detect select register - - - 0 0 0 0 0 c6 event smi status register - - - 0 0 0 0 0 cb event 2 make code register 0 0 0 0 0 0 0 0 cc event 1 make code register 0 0 0 0 0 0 0 0 cd event 0 make code register 0 0 0 0 0 0 0 0 ce event prefix code register 1 1 1 0 0 0 0 0 cf event kbc control register 0 1 - - - - - - d0 gpio2 output enable register 0 0 0 0 0 0 0 0 d1 gpio2 output data register 0 0 0 0 0 0 0 0 d2 gpio2 pin status register - - - - - - - - d3 gpio2 drive enable register 0 0 0 0 0 0 0 0 d4 gpio2 pme enable register - - 0 0 0 0 - - d5 gpio2 detect edge select register - - 0 0 0 0 - - d6 gpio2 pme status register - - 0 0 0 0 - - d7 gpio2 outpute mode select register 0 0 0 0 0 0 0 0 d8 gpio2 pulse width select register 0 0 0 0 0 0 0 0 e0 gpio1 output enable register 0 0 0 0 0 0 0 0 e1 gpio1 output data register 0 0 0 1 1 1 1 1 e2 gpio1 pin status register - - - - - - - - e3 gpio1 drive enable register 0 0 0 0 0 0 0 0 f0 gpio output enable register 0 0 0 0 0 0 0 0 f1 gpio output data register 1 1 1 1 1 1 1 1 f2 gpio pin status register - - - - - - - - f3 gpio drive enable register 0 0 0 0 0 0 0 0 wdt device configuration registers (ldn 0x07) register 0x[hex] register name default value msb lsb 30 wdt device enable register - - - - - - - 0 60 base address high register 0 0 0 0 0 0 0 0 61 base address low register 0 0 0 0 0 0 0 0 f0 wdtrst# output enable register 0 - - - 0 0 1 1 f2 reserved - - - - - - - - f3 rserved - - - - - - - - f4 reserved - - - - - - - - f5 wdt unit select register - 0 0 0 0 0 0 0 f6 wdt count register 0 0 0 0 1 0 1 0 f7 watchdog timer pme register 0 0 0 - - - - - cir configuration register (ldn 0x08)
dec, 2010 v0.18p 46 F71808A register 0x[hex] register name default value msb lsb 30 cir device enable register - - - - - - - 0 60 base address high register 0 0 0 0 0 0 0 0 61 base address low register 0 0 0 0 0 0 0 0 70 cir irq channel select register - - - - 0 0 0 0 f0 reserved - - - - - - - - f1 reserved - - - - - - - - f8 reserved 0 0 0 0 0 0 0 0 f9 reserved 0 0 0 0 0 0 0 0 fa reserved 1 0 0 0 0 0 0 0 fb reserved 0 0 1 1 1 0 1 1 fc reserved 0 0 0 0 0 0 0 0 fd reserved 0 0 0 0 0 0 0 0 fe reserved 0 0 0 0 0 0 0 0 pme, acpi, power saving device configuration registers (ldn 0x0a) register 0x[hex] register name default value msb lsb 30 pme device enable register - - - - - - - 0 f0 pme event enable register 1 0 0 0 0 - - 0 - f1 pme event status register 1 - - - - - - - - f2 pme event enable register 2 - - - 0 - - 0 0 f3 pme event status register 2 - - - - - - - - f4 keep last state select register 0 0 0 0 0 1 1 0 f5 vddok delay select register 0 0 1 1 1 1 0 0 f6 pcirst control register 0 0 0 1 1 1 1 1 f7 vsbgate control register - - - - 0 - 0 0 f8 led vcc control register 0 0 0 0 0 0 0 0 f9 led vsb control register - 0 0 0 0 0 0 0 fa led vcc/vsb additional contro l register - 0 0 0 - 0 0 0 fd reserved - - - - - - - - e0 eup enable register 0 - - 1 - - 0 0 e1 eup control register 1 1 1 0 0 0 0 0 0 e2 eup control register 2 - - 0 0 - - 0 0 e3 eup psin debounce register 0 0 0 1 0 0 1 1 e4 eup rsmrst debounce register 0 0 0 0 1 0 0 1 e5 eup psout debounce register 1 1 0 0 0 1 1 1 e6 eup pson debounce register 0 0 0 0 1 0 0 1
dec, 2010 v0.18p 47 F71808A e7 eup deep s5 delay register 0 1 1 0 0 0 1 1 e8 eup wakeup event enable register 1 - 0 0 - 0 0 0 0 e9 eup deep s3 delay register 0 0 0 0 1 1 1 1 ec eup wakeup event enable register 2 0 0 0 0 0 0 0 0 ed eup watchdog control register 0 0 0 0 - - 0 0 ee eup watchdog time register 0 0 0 0 0 0 0 0 8.1 global control registers 8.1.1 software reset register ? index 02h bit name r/w default description 7-1 reserved - - reserved 0 soft_rst r/w 0 write 1 to reset the r egister and device powered by vdd (vcc). 8.1.2 logic device number register (ldn) ? index 07h bit name r/w default description 7-0 ldn r/w 00h 01h: select uart device c onfiguration registers. 04h: select hardware monitor dev ice configuration registers. 05h: select kbc device co nfiguration registers. 06h: select gpio device c onfiguration registers. 07h: select wdt device c onfiguration registers. 08h: select cir device co nfiguration registers. 0ah: select pme, acpi & power saving device configuration registers. 8.1.3 chip id register ? index 20h bit name r/w default description 7-0 chip_id1 r 10h chip id 1. 8.1.4 chip id register ? index 21h bit name r/w default description 7-0 chip_id2 r 01h chip id2. 8.1.5 vendor id register ? index 23h bit name r/w default description 7-0 vendor_id1 r 19h vendor id 1 of fintek devices.
dec, 2010 v0.18p 48 F71808A 8.1.6 vendor id register ? index 24h bit name r/w default description 7-0 vendor_id2 r 34h vendor id 2 of fintek devices. 8.1.7 software power down register ? index 25h bit name r/w default description 7-2 reserved - - reserved. 1 softpd_ur r/w 0 write ?1? to disable uart clock. 0 reserved - - reserved. 8.1.8 uart irq sharing register ? index 26h bit name r/w default description 7 clk24m_sel r/w 0 0: clkin is 48mhz 1: clkin is 24mhz 6-3 reserved - - reserved. 2 tx_del_1bit r/w 0 0: uart tx transmits data immediately after writing thr. 1: uart tx transmits data one bit time after writing thr. 1-0 reserved - - reserved. 8.1.9 configuration port select register ? index 27h bit name r/w default description 7-5 reserved - - reserved. 4 port_4e_en r/w - 0: the configuration register port is 2e/2f. 1: the configuration register port is 4e/4f. this register is power on trapped by sout/ config4e_2e. pull down to select port 2e/2f. 3-2 reserved - - reserved. 1 pwok_mode r/w - 0: pwok follows intel sequence. 1: pwok follows amd sequence. this register is power on trapped by gpio04/pwm/rts#/strap_pwrok. pull down to select intel sequence.
dec, 2010 v0.18p 49 F71808A 0 timing_en r/w 1 0: disable timing sequence. 1: enable timing sequence. 8.1.10 multi-function select register 0 ? index 28h (powered by vsb3v) bit name r/w default description 7 gpio07_alt_en r/w 0 gpio07_alt_en and ur_gp_en[1:0] are used to select the function of pin 60. the function select signal is shown below. func_sel = { gpio07_alt_en, ur_gp_en[1:0]} 000, 001, 010: sin 011: gpio07 1xx: cirwb# 6 reserved - - reserved 5 gpio05_alt_en r/w 0 gpio05_alt_en and ur_gp_en[1:0] are used to select the function of pin 58. the function select signal is shown below. func_sel = { gpio05_alt_en, ur_gp_en[1:0]} 000: dsr# 001, 010, 011: gpio05 1xx: beep 4 gpio04_alt_en r/w 0 gpio04_alt_en and ur_gp_en[0] are used to select the function of pin 57. the function select signal is shown below. func_sel = { gpio04_alt_en, ur_gp_en[0]} 00: rts# 01: gpio04 1x: pwm 3 gpio03_alt_en r/w 0 gpio03_alt_en and ur_gp_en[1:0] are used to select the function of pin 56. the function select signal is shown below. func_sel = { gpio03_alt_en, ur_gp_en[1:0]} 000: dtr# 001, 010, 011: gpio03 1xx: cirtx
dec, 2010 v0.18p 50 F71808A 2 gpio02_alt_en r/w 0 gpio02_alt_en and ur_gp_en[1:0] are used to select the function of pin 55. the function select signal is shown below. func_sel = { gpio02_alt_en, ur_gp_en[1:0]} 000: cts# 001, 010, 011: gpio02 1xx: cirled 1 gpio01_alt_en r/w 0 gpio01_cirwb_en, gpio01_alt_en and ur_gp_en[1:0] are used to select the function of pin 54. the function select signal is shown below. if gpio01_ cirwb_en is set to 1, the pin function is cirwb#. if gpio01_cirwb_en is set to 0, the pin function is as below. 000: ri# 001, 010, 011: gpio01 1xx: ovt# 0 gpio00_alt_en r/w 0 gpio00_ a lt_en and ur_gp_en[1:0] are used to select the function of pin 53. the function select signal is shown below. func_sel = { gpio00_alt_en, ur_gp_en[1:0]} 000: dcd# 001, 010, 011: gpio00 1xx: sda 8.1.11 multi-function select register 1 ? index 29h (powered by vsb3v) bit name r/w default description 7-6 ur_gp_en r/w 3h uart/gpio function select. ur_gp_en needs to combine with the additional pin function select in index 28h if pin function is more than 3. please refer to index 28h for more detail. 00 : all pins for uart 01: sin/sout enable, other pins are gpios. 10: sin/sout/rts# enable, other pins are gpios. 11: all pins are gpios. 5 gpio35_en r/w 0 fanin2 /gpio35 function select. 0: the pin function is fanin2 1: the pin function is gpio35
dec, 2010 v0.18p 51 F71808A 4 gpio34_en r/w 0 fanctl2/gpio34 function select. 0: the pin function is fanctl2. 1: the pin function is gpio34. 3 reserved - - reserved 2 wdrst_gp25_e n r/w 0 gpio25/ledvcc/wdrst# function select. if gp25_wdrst_en is set to 1, the pin function is wdrst#. if gp25_wdrst_en is set to 0, the pin function is selected by gpio25_en. 0: the pin function is ledvcc. 1: the pin function is gpio25. 1 gpio31_en r/w 0 vldt_en/gpio31/sda2 function select. 0: the pin function is vldt_en 1: the pin function is gpio31 this register only has effect when tsi_sda2_pin_en is ?0?. 0 gpio30_en r/w 0 vcore_en/gpio30 function select. 0: the pin function is vcore_en 1: the pin function is gpio30 8.1.12 multi-function select register 2 ? index 2ah (powered by vsb3v) bit name r/w default description 7 gp01_cirwb_en r/w 0 gpio01_cirwb_en, gpio01_alt_en and ur_gp_en[1:0] are used to select the function of pin 54. the function select signal is shown below. if gpio01_cirwb_en is set to 1, the pin function is cirwb#. if gpio01_cirwb_en is set to 0, the pin function is as below. func_sel = {gpio01_alt _en, ur_gp_en[1:0]} 000: ri# 001, 010, 011: gpio01 1xx: ovt#
dec, 2010 v0.18p 52 F71808A 6 gp26_wdrst_e n r/w 0 slp_sus#/wdrst#/resetcon#/gpio26 function select. if gp26_wdrst_en is set to 1, t he pin function is wdtrst#. i f gp26_wdrst_en is set to 0, t he pin function is as below. func_sel = {gp26_alt_en, gp26_wdrst_en, gpio26_en} 1xx : the pin function is slp_sus# 01x: the pin function is wdrst# 000: the pin function is resetcon#. 001: the pin function is gpio26. 5 dpwrok_gp23_ en r/w 1 dpwrok/gpio23/wdtrst#/fanin3 function select. the function si controlled by {dpwrok_gp23_en, fanin3_gp_en, gpio23_en} 1xx: the pin function is dpwrok. 01x: the pin function is fanin3. 001: the pin function is gpio23. 000: the pin function is wdtrst#. 4 psout_gp_en r/w 0 psout#/gpio14 function select. 0: the pin function is psout#. 1: the pin function is gpio14. 3 fanin3_gp23_en r/w 0 dpwrok/gpio23/wdtrst#/fanin3 function select. the function si controlled by {dpwrok_gp23_en, fanin3_gp_en, gpio23_en} 1xx: the pin function is dpwrok. 01x: the pin function is fanin3. 001: the pin function is gpio23. 000: the pin function is wdtrst#. 2 fanin3_gp21_en r/w 0 gpio21/ovt#/fanin3 function select. the function is controlled by {fanin3_gp21_en, gpio21_en} 1x: the pin function is fanin3. 01: the pin function is gpio21. 00: the pin function is ovt#. the priority of fanin3_gp23_en is higher than fanin3_gp21_en.
dec, 2010 v0.18p 53 F71808A 1 kb_gp_en r/w 0 kclk/gpio11/ovt# and kdata/gpio10/fanin3 function select. pin 14 is controlled by {gp10_alt_en(index 2ch_bit0), kb_gp_en} 1x: the pin function is fanin3. 01: the pin function is gpio10. 00: the pin function is kdata. pin 15 is controlled by {gp11_alt_en(index 2ch_bit1), kb_gp_en} 1x: the pin function is ovt#. 01: the pin function is gpio11. 00: the pin function is kclk. 0 mo_gp_en r/w 1 sus_ack#/mdata/gpio12 and sus_warn#/mclk/gpio13/cirwb# function select. pin 16 is controlled by {gp12_alt_en(index 2ch_bit2), mo_gp_en} 1x: the pin function is sus_ack#. 01: the pin function is gpio12. 00: the pin function is mdata. pin 17 is controlled by {gp13_alt_en(index 2ch_bit3), mo_gp_en} 11: the pin function is sus_warn#. 10: the pin function is cirwb#. 01: the pin function is gpio13. 00: the pin fcuntion is mclk. 8.1.13 multi-function select register 3 ? index 2bh (powered by vbat) bit name r/w default description 7 gpio27_en r/w 0 psin#/gpio27 function select. 0: the pin function is psin#. 1: the pin function is gpio27.
dec, 2010 v0.18p 54 F71808A 6 gpio26_en r/w 1 slp_sus#/wdrst#/resetcon#/gpio26 function select. if gp26_wdrst_en is set to 1, t he pin function is wdtrst#. i f gp26_wdrst_en is set to 0, t he pin function is as below. func_sel = {gp26_alt_en, gpio26_en} 00: the pin function is resetcon#. 01: the pin function is gpio26. 1x: the pin function is slp_sus# 5 gpio25_en r/w 1 gpio25/ledvcc/wdrst# function select. if gp25_wdrst_en is set to 1, the pin function is wdrst#. if gp25_wdrst_en is set to 0, the pin function is selected by gpio25_en. 0: the pin function is ledvcc. 1: the pin function is gpio25. 4 gpio24_en r/w 1 gpio24/ledvsb function select. 0: the pin function is ledvsb. 1: the pin function is gpio24. 3 gpio23_en r/w 1 dpwrok/gpio23/wdtrst#/fanin3 function select. the function si controlled by {dpwrok_gp23_en, fanin3_gp_en, gpio23_en} 1xx: the pin function is dpwrok. 01x: the pin function is fanin3. 001: the pin function is gpio23. 000: the pin function is wdtrst#. 2 gpio22_en r/w 1 gpio22/pwm function select. 0: the pin function is pwm. 1: the pin function is gpio22. 1 gpio21_en r/w 1 gpio21/ovt#/fanin3 function select. the function is controlled by {fanin3_gp21_en, gpio21_en} 1x: the pin function is fanin3. 01: the pin function is gpio21. 00: the pin function is ovt#. the priority of fanin3_gp23_en is higher than fanin3_gp21_en.
dec, 2010 v0.18p 55 F71808A 0 gpio20_en r/w 1 gpio20/pme# function select. 0: the pin function is pme#. 1: the pin function is gpio20. 8.1.14 multi-function select register 4 ? index 2ch (powered by vbat) bit name r/w default description 7 dsw_alt_en r/w 0 set this bit ?1? to enable vin3 (pin 45) function as sus_warn# and pin 49 function as sus_ack#. 6 k8_chk_s0 r/w 0 0: amd timing sequence does not check s0/s3/s5 state. 1: amd timing sequence checks s0/s3/s5 state. 5 reserved - - reserved 4 gp26_alt_en r/w 1 slp_sus#/wdrst#/resetcon#/gpio26 function select. if gp26_wdrst_en is set to 1, t he pin function is wdtrst#. i f gp26_wdrst_en is set to 0, t he pin function is as below. func_sel = {gp26_alt_en, gp26_wdrst_en, gpio26_en} 1xx : the pin function is slp_sus# 01x: the pin function is wdrst# 000: the pin function is resetcon#. 001: the pin function is gpio26. 3 gp13_alt_en r/w 1 sus_warn#/mclk/gpio13/cirwb# function select. pin 17 is controlled by {gp13_alt_en, mo_gp_en (index 2ah_bit0)} 11: the pin function is sus_warn#. 10: the pin function is cirwb#. 01: the pin function is gpio13. 00: the pin fcuntion is mclk. 2 gp12_alt_en r/w 1 sus_ack#/mdata/gpio12 and function select. pin 16 is controlled by {gp12_alt_en, mo_gp_en (index 2ah_bit0)} 1x: the pin function is sus_ack#. 01: the pin function is gpio12. 00: the pin function is mdata.
dec, 2010 v0.18p 56 F71808A 1 gp11_alt_en r/w 0 kclk/gpio11/ovt# function select. pin 15 is controlled by {gp11_alt_en, kb_gp_en (index 2ah_bit1)} 1x: the pin function is ovt#. 01: the pin function is gpio11. 00: the pin function is kclk. 0 gp10_alt_en r/w 0 kdata/gpio10/fanin3 function select. pin 14 is controlled by {gp10_alt_en, kb_gp_en (index 2ah_bit1)} 1x: the pin function is fanin3. 01: the pin function is gpio10. 00: the pin function is kdata. 8.1.15 wakeup control register ? index 2dh (powered by vbat) bit name r/w default description 7 reserved - - reserved 6 vsbok_hys_dis r/w 0 0: enable vsbok detect hysteresis. 1: disable vsbok detect hysteresis. 5 vsbok_lvl_sel r/w 1 0: vsb3v power good level is 3.05 v and not good level is 2.95v. 1: vsb3v power good level is 2.8v and not good level is 2.5v. by vsbok_hys_dis and vsbok_lvl_sel, rsmrst# falling edge could be determined: 00: when vsb3v is lower than 2.95v. 01: when vsb3v is lower than 2.5v. 10: when vsb3v is lower than 3.05v. 11: when vsb3v is lower than 2.8v. 4 key_sel_add r/w 0 this bit is added to add more wakeup key function. 3 wakeup_en r/w 1 0: disable keyboard/mouse wake up. 1: enable keyboard/mouse wake up.
dec, 2010 v0.18p 57 F71808A 2-1 key_sel r/w 00 this registers select the key board wake up key. accompanying with key_sel_add, there are eight wakeup keys: key_s el_ad d key _sel wakeup key 0 00 ctrl + esc 0 01 ctrl + f1 0 10 ctrl + user_w akeup_code (space) 0 11 any key 1 00 windows wakeup 1 01 windows power 1 10 ctrl + alt + user_wakeup_code (space) 1 11 user_wakeup_ code (space) 0 mo_sel r/w 0 this register select the mouse wake up key. 0: wake up by click. 1: wake up by click and movement. 8.2 uart registers (ldn 0x01) 8.2.1 uart 1 device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 ur_en r/w 1 0: disable uart. 1: enable uart. 8.2.2 base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 03h the msb of uart base address.
dec, 2010 v0.18p 58 F71808A 8.2.3 base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w f8h the l sb of uart base address. 8.2.4 irq channel select register ? index 70h bit name r/w default description 7-4 reserved - - reserved. 3-0 selurirq r/w 4h select the irq channel for uart. 8.2.5 rs485 enable register ? index f0h bit name r/w default description 7-6 reserved - - reserved. 5 rs485_inv - - write ?1? will invert the rts# if rs485_en is set. 4 rs485_en r/w 0 0: rs232 driver. 1: rs485 driver. rts# drive high when transmitting data, otherwise is kept low. 3-0 reserved - - reserved. 8.3 hardware monitor register (ldn 0x04) 8.3.1 hardware monitor configuration registers hardware monitor device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 hm_en r/w 1 0: disable hardware monitor. 1: enable hardware monitor. base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 02h the msb of ha rdware monitor base address.
dec, 2010 v0.18p 59 F71808A base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w 95h the lsb of hardware monitor base address. irq channel select register ? index 70h bit name r/w default description 7-4 reserved - - reserved. 3-0 selhmirq r/w 0000 select the irq channel for hardware monitor. 8.3.2 device registers before the device registers, the following is a register map order which shows a summary of all registers. please refer each one register if you want more detail information. register cr01 ~ cr03 ? configuration registers register cr0a ~ cr0f ? peci / tsi control register register cr10 ~ cr3f ? voltage setting register register cr40~ cr4f ? peci master control register register cr60 ~ cr8e ? temperature setting register register cr90 ~ crdf ? fan control setting register ? fan1 detail setting cra0 ~ craf ? fan2 detail setting crb0 ~ crbf ? fan3 detail setting crc0 ~ crcf 8.3.2.1 configuration register ? index 01h bit name r/w default description 7-3 reserved - - reserved 2 power_down r/w 0 hardware monitor function power down. 1 fan_start r/w 1 set one to enable startup of fan monitoring operations; a zero puts the part in standby mode. 0 v_t_start r/w 1 set one to enable startup of temperature and voltage monitoring operations; a zero puts the part in standby mode. 8.3.2.2 configuration register ? index 02h bit name r/w default description 7 reserved - - reserved 6 case_beep_en r/w 0 0: disable case open event output via beep. 1: enable case open event output via beep.
dec, 2010 v0.18p 60 F71808A 5-4 ovt_mode r/w 0 00: the ovt# will be low active level mode. 01: the ovt# will be low active pulse mode. 10: the ovt# will indicate by 1hz led function. 11: the ovt# will indicate by (400/800hz) beep output. 3 reserved - - reserved 2 case_smi_en r / w 0 0: disable case open event output via pme. 1: enable case open event output via pme. 1-0 reserved - - reserved 8.3.2.3 configuration register ? index 03h bit name r/w default description 7-1 reserved - - reserved 0 case_sts r/w 1 case open status, write 1 to clear if case o pen event cleared. 8.3.2.4 configuration register ? index 08h bit name r/w default description 7-1 smbus_addr r/w 7?h26 when amd tsi or intel pch smbus is enabled, this byte is used as smbus_addr. smbus_addr [7:1] is the slave address sent by the embedded master to fetch the temperature. 0 reserved - - reserved 8.3.2.5 configuration register ? index 0ah bit name r/w default description 7-6 func_sel_add r/w 0 a dditional function select bits to combine with func_sel[1:0] for selecting the function of peci/amd tsi/intel ibex. 5-4 reserved - - reserved. 3-2 vtt_sel r/w 0 peci (vtt) voltage select. 00: vtt is 1.23v 01: vtt is 1.13v 10: vtt is 1.00v 11: vtt is 1.00v
dec, 2010 v0.18p 61 F71808A 1-0 func_sel r/w 0 func_sel[1:0] combine with func_sel_add[1:0] to select peci / amd tsi / intel ibex functi ons. the new function select is show below. new_func_sel = {func_sel_add[1:0], func_sel[1:0]} 0000: amd tsi/intel ibex/ peci are not enable 0001: amd tsi (pin51 is used as sda) 0010: peci 0011: intel ibex (pin51 is used as sda) x100: peci + intel ibex (p in50 is used as sda) x101: amd tsi (pin50 is uesd as sda) x110: peci + amd tsi (pin50 is uesd as sda) x111: intel ibex (pin50 is uesd as sda) 1000: peci + intel ibex (p in53 is used as sda) 1001: amd tsi (pin53 is uesd as sda) 1010: peci + amd tsi (pin53 is uesd as sda) 1011: intel ibex (pin53 is uesd as sda) 8.3.2.6 configuration register ? index 0bh bit name r/w default description 7-4 cpu_sel r/w 0 select the intel cpu socket number. 0000: no cpu presented. peci host will use ping() command to find cpu address. 0001: cpu is in socket 0, i.e. peci address is 0x30. 0010: cpu is in socket 1, i.e. peci address is 0x31. 0100: cpu is in socket 2, i.e. peci address is 0x32. 1000: cpu is in socket 3, i.e. peci address is 0x33. otherwise are reserved. 3-1 reserved - - reserved. 0 domain1_en r /w 0 if the cpu selected is dual core. set this register 1 to read the temperature of domain1. this bit is also used to send a domain1 peci3.0 command if peci is used as a peci master. 8.3.2.7 configuration register ? index 0ch bit name r/w default description
dec, 2010 v0.18p 62 F71808A 7-0 tcc_temp r/w 55h tcc activation temperature. when peci is enabled, the absolute value of cpu temperature is calculated by the equation: cpu_temp = tcc_temp + peci reading. when amd tsi or intel pch smbus is enabled, this byte is used as the offset to be added to the temperature reading of cpu. the range of this register is -128 ~ 127. 8.3.2.8 configuration register ? index 0dh bit name r/w default description 7-0 tsi_offset r/w 00h when peci and amd tsi/intel ibex are enabled at the same time, this byte is used as the offset to be added to the cpu temperature reading of amd_tsi/inte l ibex. to using this byte as offset of amd tsi/intel ibex cpu temperature reading, the tsi_offset_sel in cr0f must be set to 1. the range of this register is -128 ~ 127. 8.3.2.9 configuration register ? index 0fh bit name r/w default description 7 tsi_lv_sel r/w 0 set this bit to select the scl/sda input level. 0: ttl level 1: low voltage input level (vih=0.9v, vil=0.6v) 6 t si_offset_sel r/w 0 set this bit to select the offset of amd tsi/intel ibex. 0: tcc_temp in cr0c 1: tsi_offset in cr0d 5 reserved r/w 1 reserved. 4 tsi03_sel r/w 0 if this bit is set to 1, cr7b is able to be written and can also be used to control fan. 3 tsi02_sel r/w 0 if this bit is set to 1, cr7c is able to be written and can also be used to control fan. 2 tsi01_sel r/w 0 if this bit is set to 1, cr7d is able to be written and can also be used to control fan.
dec, 2010 v0.18p 63 F71808A 1-0 dig_rate_sel r/w 0 the accessing rate for amd tsi/intel ibex/peci to access external slave device. 0: access slave device after 1 diode temperature conversion 1: access slave device after 2 diode temperature conversion 2: access slave device after 3 diode temperature conversion 3: access slave device after 4 diode temperature conversion voltage setting 8.3.2.10 voltage reading and limit register ? index 20h- 3fh address attribute default value description 20h ro -- vcc3v reading. the unit of reading is 8mv. 21h ro -- v1 (vcore) reading. the unit of reading is 8mv. 22h ro -- v2 reading. the unit of reading is 8mv. 23h ro -- v3 reading. the unit of reading is 8mv. 24h -- -- reserved 25h -- -- reserved 26h -- -- reserved 27h ro -- vsb3v reading. the unit of reading is 8mv. 28h ro -- vbat reading. the unit of reading is 8mv. 29~2ch -- -- reserved 2dh ro -- fan1 present fan duty reading 2eh ro -- fan2 present fan duty reading 2fh ro -- fan3 present fan duty reading 30~3fh -- -- reserved peci 3.0 command and register 8.3.2.11 peci configuration register ? index 40h bit name r/w default description 7 r diamsr_cmd_e n r/w 0 when peci temperature monitoring is enabled, set this bit 1 will generate a rdiamsr() command before a gettemp() command. 6 c3_update_en r/w 0 if rdiamsr_cmd_en is not set to 1, the temperature data is not allowed to be updated when the co mpletion code of rdiamsr() is 0x82. 5-4 reserved r - reserved 3 c3_ptemp_en r/w 0 set this bit 1 to enable updateing positive value of temperature if the completion code of rdiamsr() is 0x82.
dec, 2010 v0.18p 64 F71808A 2 c0_ptemp_en r/w 0 set this bit 1 to enable updating positive value of temperature if the completion code of rdiamsr() is not 0x82 and the bit 8 of completion code is not 1 either. 1 c3_all0_en r/w 0 set this bit 1 to enable updating temperature value 0x0000 if the completion code of rdiamsr() is 0x82. 0 c0_all0_en r/w 0 set this bit 1 to enable updating temperature value 0x0000 if the completion code of rdiamsr() is not 0x82 and the bit 8 of completion code is not 1 either. 8.3.2.12 peci master control register ? index 41h bit name r/w default description 7 peci_cmd_star t w - write 1 to this bit to start a peci command when using as a peci master. (peci_pending must be set to 1) 6-5 reserved r - reserved 4 peci_pending r/w 0 set this bit 1 to stop monitoring peci temperature. 3 reserved r - reserved 2-0 peci_cmd r/w 3?h0 peci command to be used by peci master. 000: ping() 001: getdib() 010: gettemp() 011: rdiamsr() 100: rdpkgconfig() 101: wrpkgconfig() others: reserved 8.3.2.13 peci master status register ? index 42h bit name r/w default description 7-3 reserved r - reserved 2 abort_fcs r/w c - this bit is the abort fcs status of peci master commands. write this bit 1 or read this byte will clear this bit to 0. 1 peci_fcs_err r/w c - this bit is the fcs error status of peci master commands. write this bit 1 or read this byte will clear this bit to 0. 0 peci_finish r/w c - this bit is the command finish status of peci master commands. write this bit 1 or read this by te will clear this bit to 0. 8.3.2.14 peci master data0 register ? index 43h bit name r/w default description 7-0 peci_data0 r/w 0 for rdiamsr(), rdpkgconfig() and wrpkgconfig() command, this byte represents ?host id[7:1] & retry[0]?. please refer to peci interface specification for more detail. 8.3.2.15 peci master data1 register ? index 44h bit name r/w default description 7-0 peci_data1 r/w 0 for rdiamsr() , this byte represents ?processor id?. for rdpkgconfig() and wrpkgconfig() , this byte represents ?index?. please refer to peci interface specification for more detail.
dec, 2010 v0.18p 65 F71808A 8.3.2.16 peci master data2 register ? index 45h bit name r/w default description 7-0 peci_data2 r/w 0 for rdiamsr(), this byte is the least significant byte of ?msr address?. for rdpkgconfig() and wrpkgconfig(), this byte is the least significant byte of ?parameter?. please refer to peci interface specification for more detail. 8.3.2.17 peci master data3 register ? index 46h bit name r/w default description 7-0 peci_data3 r/w 0 for rdiamsr(), this byte is the most significant byte of ?msr address?. for rdpkgconfig() and wrpkgconfig(), this byte is the most significant byte of ?parameter?. please refer to peci interface specification for more detail. 8.3.2.18 peci master data4 register ? index 47h bit name r/w default description 7-0 peci_data4 r/w 0 for getdib() , this byte represents ?device info? for gettemp(), this byte represents the least significant byte o f temperature. for rdiamsr() and rdpkgconfig() , this byte is ?completion code?. for wrpkgconfig(), this byte represents ?data[7:0]? 8.3.2.19 peci master data5 register ? index 48h bit name r/w default description 7-0 peci_data5 r/w 0 for getdib() , this byte represents ?revision number? for gettemp(), this byte represents the most significant byte o f temperature. for rdiamsr() and rdpkgconfig() , this byte represents ?data[7:0]? for wrpkgconfig(), this byte represents ?data[15:8]? 8.3.2.20 peci master data6 register ? index 49h bit name r/w default description 7-0 peci_data6 r/w 0 for rdiamsr() and rdpkgconfig() , this byte represents ?data[15:8]?. for wrpkgconfig(), this byte represents ?data[23:16]? 8.3.2.21 peci master data7 register ? index 4ah bit name r/w default description 7-0 peci_data7 r/w 0 for rdiamsr() and rdpkgconfig() , this byte represents ?data[23:16]?. for wrpkgconfig(), this byte represents ?data[31:24]? 8.3.2.22 peci master data8 register ? index 4bh bit name r/w default description
dec, 2010 v0.18p 66 F71808A 7-0 peci_data8 r/w 0 for rdiamsr() and rdpkgconfig() , this byte represents ?data[31:24]?. for wrpkgconfig(), this byte represents ?aw fcs? 8.3.2.23 peci master data9 register ? index 4ch bit name r/w default description 7-0 peci_data9 r/w 0 for rdiamsr(), this byte represents ?data[39:32]?. for wrpkgconfig(), this byte represents ?completion code? 8.3.2.24 peci master data10 register ? index 4dh bit name r/w default description 7-0 peci_data10 r/w 0 for rdiamsr(), th is byte represents ?data[47:40]?. 8.3.2.25 peci master data11 register ? index 4eh bit name r/w default description 7-0 peci_data11 r/w 0 for rdiamsr(), th is byte represents ?data[55:48]?. 8.3.2.26 peci master data12 register ? index 4fh bit name r/w default description 7-0 peci_data12 r/w 0 for rdiamsr(), th is byte represents ?data[63:56]?. temperature setting 8.3.2.27 temperature pme# enable register ? index 60h bit name r/w default description 7 reserved r - reserved 6 en_ t2_ ovt_pme r/w 0 if set this bit to 1, pme# si gnal will be issued when temp2 exceeds ovt setting. 5 en_ t1_ ovt_pme r/w 0 if set this bit to 1, pme# si gnal will be issued when temp1 exceeds ovt setting. 4 reserved r - reserved 3 reserved r - reserved 2 en_ t2_exc_pme r/w 0 if set this bit to 1, pme# si gnal will be issued when temp2 exceeds high limit setting. 1 en_ t1_exc_pme r/w 0 if set this bit to 1, pme# si gnal will be issued when temp1 exceeds high limit setting. 0 reserved r - reserved
dec, 2010 v0.18p 67 F71808A 8.3.2.28 temperature interrupt status register ? index 61h bit name r/w default description 7 reserved - - reserved 6 t2_ovt _sts r/w 0 a one indicates temp2 temperature sensor has exceeded ovt limit or below the ?ovt limit ?hysteresis?. write 1 to clear this bit, write 0 will be ignored. 5 t1_ovt _sts r/w 0 a one indicates temp1 temperature sensor has exceeded ovt limit or below the ?ovt limit ?hysteresis?. write 1 to clear this bit, write 0 will be ignored. 4 reserved - - reserved 3 reserved - - reserved 2 t2_exc _sts r/w 0 a one indicates temp2 temperature sensor has exceeded high limit or below the ?high limit ?hysteresis? limit. write 1 to clear this bit, write 0 will be ignored. 1 t1_exc _sts r/w 0 a one indicates temp1 temperature sensor has exceeded high limit or below the ?high limit ?hy steresis? limit. write 1 to clear this bit, write 0 will be ignored. 0 reserved - - reserved 8.3.2.29 temperature real time status register ? index 62h bit name r/w default description 7 reserved - - reserved 6 t2_ovt r/w 0 set when the temp2 exceeds the ovt limit. clear when the temp2 is below the ?ovt limit ?hysteresis? temperature. 5 t1_ovt r/w 0 set when the temp1 exceeds the ovt limit. clear when the temp1 is below the ?ovt limit ?hysteresis? temperature. 4 reserved - - reserved 3 reserved - - reserved 2 t2_exc r/w 0 set when the temp2 exceeds the high limit. clear when the temp2 is below the ?high limit ?hysteresis? temperature. 1 t1_exc r/w 0 set when the temp1 exceeds the high limit. clear when the temp1 is below the ?high limit ?hysteresis? temperature. 0 reserved - - reserved 8.3.2.30 temperature beep enable register ? index 63h bit name r/w default description 7 reserved - - reserved
dec, 2010 v0.18p 68 F71808A 6 en_ t2_ ovt_beep r/w 0 if set this bit to 1, beep signal will be issued when temp2 exceeds ovt limit setting. 5 en_ t1_ ovt_beep r/w 0 if set this bit to 1, beep signal will be issued when temp1 exceeds ovt limit setting. 4 reserved - - reserved 3 reserved - - reserved 2 en_ t2_exc_beep r/w 0 if set this bit to 1, beep signal wi ll be issued when temp2 exceeds high limit setting. 1 en_ t1_exc_beep r/w 0 if set this bit to 1, beep signal wi ll be issued when temp1 exceeds high limit setting. 0 reserved - - reserved 8.3.2.31 t1 over-ovt and over-high limit temperature select register ? index 64h bit name r/w default description 7-6 reserved - - reserved 5-4 t1_ovt_temp_s el r/w 0 set this bit to select the temperature source of t1_ovt_limit. 00: diode t1 temperature 01: peci temperature 10: cpu temperature of amd tsi or intel ibex 11: max. temperature of intel ibex 3-2 reserved - - reserved 1-0 t1_high_temp_ sel r/w 0 set this bit to select the temperature source of t1_high_limit. 00: diode t1 temperature 01: peci temperature 10: cpu temperature of amd tsi or intel ibex 11: max. temperature of intel ibex 8.3.2.32 ovt output enable register 1 ? index 66h bit name r/w default description 7-3 reserved - - reserved 2 en_t2_ovt r/w 0 enable over temperature (ovt) mechanism of temperature2. 1 en_t1_ovt r/w 1 enable over temperature (ovt) mechanism of temperature1. 0 reserved - - reserved. 8.3.2.33 temperature sensor type register ? index 6bh bit name r/w default description 7-3 reserved - - reserved 2 t2_mode r/w 1 0: temp2 is connected to a thermistor. 1: temp2 is connected to a bjt. (default) 1 t1_mode r/w 1 0: temp1 is connected to a thermistor 1: temp1 is connected to a bjt.(default) 0 reserved - - reserved
dec, 2010 v0.18p 69 F71808A 8.3.2.34 temp1 limit hystersis select register -- index 6ch bit name r/w default description 7-4 temp1_hys r/w 4h limit hysteresis. (0~15 degree c) temperature and below the ( boundary ? hysteresis ). 3-0 reserved - - reserved 8.3.2.35 temp2 and temp3 limit hyst ersis select register -- index 6dh bit name r/w default description 7-4 reserved - - reserved 3-0 temp2_hys r/w 4h limit hysteresis. (0~15 degree c) temperature and below the ( boundary ? hysteresis ). 8.3.2.36 diode open status register -- index 6fh bit name r/w default description 7-6 reserved - - reserved 5 peci_open ro 0h when peci interface is enabled, it indicates an error code (0x0080 or 0x0081) is received from peci slave. 4 tsi_open ro 0h when amd tsi or intel ibex interface is enabled, it indicates the error of not receiving nack bit or a timeout occurred. 3 reserved - - reserved 2 t2_diode_open ro 0h set to 1 when external diode 2 is open or short 1 t1_diode_open ro 0h set to 1 when external diode 1 is open or short 0 reserved - - reserved 8.3.2.37 diode t1 temperature scale register -- index 7fh bit name r/w default description 7-5 reserved - - reserved 3 add r/w 0h diode t1 temperature scale selection. 1: temp. = reading value + reading value* scale t diode _ 1 _ 2 ? 0: temp. = reading value - reading value* scale t diode _ 1 _ 2 ? 2 reserved - - reserved
dec, 2010 v0.18p 70 F71808A 1-0 scale r/w 0h when add is 1, diode t1 temp. is selected by scale 00: temp. = 1 * reading value 01: temp. = 17/16 * reading value 10: temp. = 33/32 * reading value 11: temp. = 65/64 * reading value when add is 0, diode t1 temp. is selected by scale 00: temp. = 1 * reading value 01: temp. = 15/16 * reading value 10: temp. = 31/32 * reading value 11: temp. = 63/64 * reading value 8.3.2.38 temperature ? index 70h- 8fh address attribute default value description 70h reserved -- reserved 71h reserved -- reserved 72h ro -- temperature 1 reading. the unit of reading is 1 o c.at the moment of reading this register. 73h ro -- reserved 74h ro -- temperature 2 reading. the unit of reading is 1 o c.at the moment of reading this register. 75h ro -- reserved 76h ro -- reserved 77-79h ro -- reserved 7ah ro -- the data of cpu temperature from digital interface after iir filter. (available if intel ibx or amd tsi interface is enabled) 7bh ro -- the raw data of pch temperature from digital interface. (only available if intel ibx interface is enabled) 7ch ro -- the raw data of mch read from digital interface. (only available if intel ibx interface is enabled) 7dh ro -- the raw data of maximum temperature from digital interface. (only available if intel ibx interface is enabled) 7eh ro -- the data of cpu temperature from digi tal interface after iir filter. (only available if peci interface is enabled) 80h -- -- reserved 81h -- -- reserved 82h r/w 64h temperature sensor 1 ovt limit. the unit is 1 o c. 83h r/w 55h temperature sensor 1 high limit. the unit is 1 o c. 84h r/w 64h temperature sensor 2 ovt limit. the unit is 1 o c. 85h r/w 55h temperature sensor 2 high limit. the unit is 1 o c.
dec, 2010 v0.18p 71 F71808A 86-8bh -- -- reserved 8c~8dh -- -- reserved fan control setting 8.3.2.39 fan pme# enable register ? index 90h bit name r/w default description 7-3 reserved - - reserved 2 en_fan3_pme r/w 0h a one enables the corresponding interrupt status bit for pme# interrupt.. set this bit 1 to enable pme# function for fan3. 1 en_fan2_pme r/w 0h a one enables the corresponding interrupt status bit for pme# interrupt. set this bit 1 to enable pme# function for fan2. 0 en_fan1_pme r/w 0h a one enables the corresponding interrupt status bit for pme# interrupt. set this bit 1 to enable pme# function for fan1. 8.3.2.40 fan interrupt status register ? index 91h bit name r/w default description 7-3 reserved - - reserved 2 fan3_sts r/w - this bit is set when the fan3 count exceeds the count limit. write 1 to clear this bit, write 0 will be ignored. 1 fan2_sts r/w - this bit is set when the fan2 count exceeds the count limit. write 1 to clear this bit, write 0 will be ignored. 0 fan1_sts r/w - this bit is set when the fan1 count exceeds the count limit. write 1 to clear this bit, write 0 will be ignored. 8.3.2.41 fan real time status register ? index 92h bit name r/w default description 7-3 reserved - - reserved 2 fan3_exc ro - this bit set to high mean that fan3 count can?t meet expect count over than smi time(cr9f) or w hen duty not zero but fan stop over then 3 sec. 1 fan2_exc ro - this bit set to high mean that fan2 count can?t meet expect count over than smi time(cr9f) or w hen duty not zero but fan stop over then 3 sec.
dec, 2010 v0.18p 72 F71808A 0 fan1_exc ro - this bit set to high mean that fan1 count can?t meet expect count over than smi time(cr9f) or w hen duty not zero but fan stop over then 3 sec. 8.3.2.42 fan full speed enable register ? index 93h bit name r/w default description 7 reserved - - reserved. 6 full_with_t2_en r/w 0 set one will enable fan to force full speed when t2 over high limit. 5 full_with_t1_en r/w 0 set one will enable fan to force full speed when t1 over high limit. 4-0 reserved - - reserved. 8.3.2.43 fan type select register -- index 94h bit name r/w default description 7-6 reserved - - reserved. 5-4 pwm_type r/w 2?b 10 00: pwm pin output pwm mode (push pull) 01: pwm pin output voltage from dac 10: pwm pin output pwm mode (open drain) 11: reserved. 3-2 fanctl2_type r/w 2?b 1s 00: output pwm mode (push pull) to control fans. 01: use linear fan application circui t to control fan speed by fan?s power terminal. 10: output pwm mode (open drain) to control intel 4-wire fans. 11: reserved. bit 0 is power on trap by fanctl2 0: fanctl2 is pull up by external resistor. 1: fanclt2 is pull down by internal 100k resistor. 1-0 fanctl1_type (cpufan) r/w 2?b 10 00: output pwm mode (push pull) to control fans. 10: output pwm mode (open drain) to control intel 4-wire fans. s : register default values are decided by trapping. 8.3.2.44 fan1 base temperature for temp erature adjustment register -- index 94h (fan_prog_sel = 1) bit name r/w default description
dec, 2010 v0.18p 73 F71808A 7-0 fan1_base _temp r/w 0 this register is used to set the base temperature for fanctl1 temperature adjustment. the fan1 temperature is calculated according to the equation: tfan1 = tnow + (ta ? tb)*ct where tnow is selected by fan1_temp_sel_dig and fan1_temp_sel. tb is this register, ta is selected by tfan1_adj_sel and ct is selected by tfan1_adj_up_rate/tfan1_adj_dn_rate. to access this register, fan_prog_sel (cr9f[7]) must be set to ?1?. 8.3.2.45 fan1 temperature adjust rate register -- index 95h (fan_prog_sel = 1) bit name r/w default description 7 reserved - - reserved 6-4 tfan1_adj_up _rate 3?h0 this selects the weighting of the difference between ta and tb if ta is higher than tb. 3?h1: 1 (ct = 1) 3?h2: 1/2 (ct= 1/2) 3?h3: 1/4 (ct = 1/4) 3?h4: 1/8 (ct = 1/8) otherwise: 0 to access this byte, fan_pr og_sel must set to ?1?. 3 reserved - - reserved 2-0 tfan1_adj_dn _rate r/w 3?h0 this selects the weighting of the difference between ta and tb if ta is lower than tb. 3?h1: 1 (ct = 1) 3?h2: 1/2 (ct= 1/2) 3?h3: 1/4 (ct = 1/4) 3?h4: 1/8 (ct = 1/8) otherwise: 0 to access this byte, fan_pr og_sel must set to ?1?. 8.3.2.46 fan mode select register -- index 96h bit name r/w default description 7-4 reserved - - reserved.
dec, 2010 v0.18p 74 F71808A 3-2 fan2_mode r/w 1h 00: auto fan speed control, fan speed will follow different temperature by different rpm that define in 0xb6-0xbe. 01: auto fan speed control, fan speed will follow different temperature by different duty cycle (voltage) that defined in 0xb6-0xbe. 10: manual mode fan control, user can write expect rpm count to 0xb2-0xb3, and F71808Au will auto control duty cycle (pwm fan type) or voltage (linear fan type) to control fan speed. 11: manual mode fan control, user can write expect duty cycle (pwm fan type) or voltage (linear fan type) to 0xb3, and F71808Au will output this value duty or voltage to control fan speed. 1-0 fan1_mode r/w 1h 00: auto fan speed control, fan speed will follow different temperature by different rpm that define in 0xa6-0xae. 01: auto fan speed control, fan speed will follow different temperature by different duty cycle that defined in 0xa6-0xae. 10: manual mode fan control, user can write expect rpm count to 0xa2-0xa3, and F71808Au will auto control duty cycle (pwm fan type) or voltage(linear fan type) to control fan speed. 11: manual mode fan control, user can write expect duty cycle (pwm fan type) or voltage (linear fan type) to 0xa3, and F71808Au will output this value duty or voltage to control fan speed. 8.3.2.47 fan temperature adjust select re gister -- index 96h (fan_prog_sel = 1) bit name r/w default description 7-3 reserved - - reserved. 2-0 tfan1_adj_sel r/w 0h this selects which temperature to be used as ta for fan1 temperature adjustment. 000: peci (cr7eh) 001: t1 (cr72h) 01x: t2 (cr74h) 100: ibx/tsi cpu temperature (cr7ah) 101: ibx pch temperature (cr7bh) 110: ibx mch temperature (cr7ch) 111: ibx maximum temperature (cr7dh) to access this register fa n_prog_sel must set to ?1?.
dec, 2010 v0.18p 75 F71808A 8.3.2.48 auto fan1 and fan2 boundary hystersis select register -- index 98h bit name r/w default description 7-4 fan2_hys r/w 4h 0000: boundary hysteres is. (0~15 degree c) segment will change when the temperature over the boundary temperature and below the ( boundary ? hysteresis ). 3-0 fan1_hys r/w 4h 0000: boundary hysteres is. (0~15 degree c) segment will change when the temperature over the boundary temperature and below the ( boundary ? hysteresis ). 8.3.2.49 auto fan up speed update rate select register -- index 9bh (fan_prog_sel = 0) bit name r/w default description 7-4 reserved - - reserved. 3-2 fan2_ up_rate r/w 1h fan2 duty update rate: 00: 2hz 01: 5hz (default) 10: 10hz 11: 20hz 1-0 fan1(cpu) _up_rate r/w 1h fan1 duty update rate: 00: 2hz 01: 5hz (default) 10: 10hz 11: 20hz 8.3.2.50 auto fan down speed update rate se lect register -- index 9bh (fan_rate_prog_sel = 1) bit name r/w default description 7 reserved - - reserved. 6 direct_update r/w 0 0: fan duty update rate is defined in bit[5:0] 1: fan duty is updated to the desired 5-4 reserved - - reserved. 3-2 fan2_down_rate r/w 1h fan2 duty update rate: 00: 2hz 01: 5hz (default) 10: 10hz 11: 20hz 1-0 fan1_down_rate r/w 1h fan1 duty update rate: 00: 2hz 01: 5hz (default) 10: 10hz 11: 20hz 8.3.2.51 fan1 and fan2 start up duty-cycle/voltage register ? index 9ch bit name r/w default description
dec, 2010 v0.18p 76 F71808A 7-4 fan2_stop_duty r/w 5h when fan start, the fanctl2 will increase duty-cycle from 0 to this (value x 8) directly. and if fan speed is down, the fanctl 2 will decrease duty-cycle to 0 wh en the pwm duty cycle is less than this (value x 4). 3-0 fan1_stop_duty r/w 5h when fan start, the fanctl 1 will increase duty-cycle from 0 to this (value x 8 directly. and if fan speed is down, the fanctl 1 will decrease duty-cycle to 0 wh en the pwm duty cycle is less than this (value x 4). 8.3.2.52 fan power-on default duty-cycle/voltage register ? index 9eh bit name r/w default description 7-0 pwron_def_duty r/w 8?h66 fan duty value immediately loaded after vdd is powered on. 8.3.2.53 fan fault time register - index 9fh bit name r/w default description 7 fan_prog_sel r/w 0 set this bit to ?1? will enable access registers of other bank. 6 fan_mnt_sel r/w 0 set this bit to monitor a slower fan. 5-0 reserved - - reserved 8.3.2.54 fan1 index a0h- afh address attribute default value description a0h ro 8?h0f fan1 count reading (msb). at the mom ent of reading this register, the lsb will be latched. this will prevent from data updating when reading. to read the fan count correctly, read msb first and followed read the lsb. a1h ro 8?hff fan1 count reading (lsb). a2h r/w 8?h00 rpm mode(cr96 bit0=0): fan1 expect speed count val ue (msb), in auto fan mode (cr96 bit1 ? 0) this register is auto updated by hardware. duty mode(cr96 bit0=1): this byte is reserved byte. a3h r/w 8?h01 rpm mode(cr96 bit0=0): fan1 expect speed count value (lsb) or expect pwm duty, in auto fan mode this register is auto updated by hardware and read only. duty mode(cr96 bit0=1): the value programming in this byte is duty value. in auto fan mode
dec, 2010 v0.18p 77 F71808A (cr96 bit1 ? 0) this register is updated by hardware. ex: 5 ? 5*100/255 % 255 ? 100% a4h r/w 8?h03 fan1 full speed count reading (msb). at the moment of reading this register, the lsb will be latched. th is will prevent from data updating when reading. to read the fan count correctly, read msb first and followed read the lsb. a5h r/w 8?hff fan1 full speed count reading (lsb). 8.3.2.55 vt1 boundary 1 temperature register ? index a6h bit name r/w default description 7-0 bound1tmp1 r/w 3ch (60 o c) the 1 st boundary temperature for vt1 in temperature mode. when vt1 temperature is exceed this boundary, fan1 expect value will load from segment 1 register (index aah). when vt1 temperature is below this boundary ? hysteresis, fan1 expect value will load from segment 2 register (index abh). this byte is a 2?s complement value ranging from -128?c ~ 127?c. 8.3.2.56 vt1 boundary 2 temperature register ? index a7 bit name r/w default description 7-0 bound2tmp1 r/w 32h (50 o c) the 2 nd boundary temperature for vt1 in temperature mode. when vt1 temperature is exceed this boundary, fan1 expect value will load from segment 2 register (index abh). when vt1 temperature is below this boundary ? hysteresis, fan1 expect value will load from segment 3 register (index ach). this byte is a 2?s complement value ranging from -128?c ~ 127?c. 8.3.2.57 vt1 boundary 3 temperature register ? index a8 bit name r/w default description
dec, 2010 v0.18p 78 F71808A 7-0 bound3tmp1 r/w 28h (40 o c) the 3 rd boundary temperature for vt1 in temperature mode. when vt1 temperature is exceed this boundary, fan1 expect value will load from segment 3 register (index ach). when vt1 temperature is below this boundary ? hysteresis, fan1 expect value will load from segment 4 register (index adh). this byte is a 2?s complement value ranging from -128?c ~ 127?c. 8.3.2.58 vt1 boundary 4 temperature register ? index a9 bit name r/w default description 7-0 bound4tmp1 r/w 1eh (30 o c) the 4th boundary temperature for vt1 in temperature mode. when vt1 temperature is exceed this boundary, fan1 expect value will load from segment 4 register (index adh). when vt1 temperature is below this boundary ? hysteresis, fan1 expect value will load from segment 5 register (index aeh). this byte is a 2?s complement value ranging from -128?c ~ 127?c. 8.3.2.59 fan1 segment 1 speed count register ? index aah bit name r/w default description 7 - 0 sec1speed1 r /w ffh (100%) the meaning of this register is depending on the fan1_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. ex: 100% full speed: user must set this register to 0. 60% full speed: (100-60)*32/60, so user must program 21 to this reg. x% full speed: the value programming in this byte is ? (100-x)*32/x 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. 8.3.2.60 fan1 segment 2 speed count register ? index abh bit name r/w default description
dec, 2010 v0.18p 79 F71808A 7 - 0 sec2speed1 r /w d9h (85%) the meaning of this register is depending on the fan1_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. 8.3.2.61 fan1 segment 3 speed count register ? index ach bit name r/w default description 7 - 0 sec3speed1 r /w b2h (70%) the meaning of this register is depending on the fan1_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. 8.3.2.62 fan1 segment 4 speed count register ? index adh bit name r/w default description 7 - 0 sec4speed1 r /w 99h (60%) the meaning of this register is depending on the fan1_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. 8.3.2.63 fan1 segment 5 speed count register ? index aeh bit name r/w default description 7 - 0 sec5peed1 r /w 80h (50%) the meaning of this register is depending on the fan1_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. 8.3.2.64 fan1 temperature mapping select register ? index afh bit name r/w default description 7 fan1_temp_sel_dig r/w 0 this bit companying with fan1_temp_sel select the temperature source for controlling fan1.
dec, 2010 v0.18p 80 F71808A 6 reserved - 0 reserved 5 fan1_up_t_en r /w 0 set 1 to force fan1 to full speed if any temperature over its high limit. 4 fan1_interpolatio n_en r/w 1 set 1 will enable the interpolati on of the fan expect table. 3 fan1_jump_high_en r/w 1 this register controls the fan1 duty movement when temperature over highest boundary. 0: the fan1 duty will increases with the slope selected by fan1_up_rate register. 1: the fan1 duty will directly jumps to the value of sec1speed1 register. this bit only activates in duty mode. 2 fan1_jump_low_en r/w 1 this register controls the fan1 duty movement when temperature under (highest boundary ? hysteresis). 0: the fan1 duty will decreases with the slope selected by fan1_dn_rate register. 1: the fan1 duty will directly jumps to the value of sec2speed1 register. this bit only activates in duty mode. 1 - 0 fan1_temp_sel r /w 1 this registers companying with fan1_temp_sel_dig select the temperature source for controllin g fan1. the following value is comprised by {fan1_temp_sel_dig, fan1_temp_sel} 000: fan1 follows peci temperature (cr7eh) 001: fan1 follows temperature 1 (cr72h). 010: fan1 follows temperature 2 (cr74h). 011: fan1 follows temperature 3 (cr76h). 100: fan1 follows ibx/tsi cpu temperature (cr7ah) 101: fan1 follows ibx pch temperature (cr7bh). 110: fan1 follows ibx m ch temperature (cr7ch). 111: fan1 follows ibx maximum temperature (cr7dh). otherwise: reserved. 8.3.2.65 fan2 index b0h- bfh address attribute default value description
dec, 2010 v0.18p 81 F71808A b0h ro 8?h0f fan2 count reading (msb). at the mom ent of reading this register, the lsb will be latched. this will prevent from data updating when reading. to read the fan count correctly, read msb first and followed read the lsb. b1h ro 8?hff fan2 count reading (lsb). b2h r/w 8?h00 rpm mode(cr96 bit2=0): fan2 expect speed count val ue (msb), in auto fan mode(cr96 bit3 ? 0) this register is auto updated by hardware. duty mode(cr96 bit2=1): this byte is reserved byte. b3h r/w 8?h01 rpm mode(cr96 bit2=0): fan2 expect speed count value (lsb) or expect pwm duty , in auto fan mode this register is auto updated by hardware and read only. duty mode(cr96 bit2=1): the value programming in this byte is duty value. in auto fan mode(cr96 bit3 ? 0) this register is updated by hardware. ex: 5 ? 5*100/255 % 255 ? 100% b4h r/w 8?h03 fan2 full speed count reading (msb). at the moment of reading this register, the lsb will be latched. th is will prevent from data updating when reading. to read the fan count correctly, read msb first and followed read the lsb. b5h r/w 8?hff fan2 full speed count reading (lsb). 8.3.2.66 vt2 boundary 1 temperature register ? index b6h bit name r/w default description 7-0 bound1tmp2 r/w 3ch (60 o c) the 1 st boundary temperature for vt2 in temperature mode. when vt2temperature is exceed this boundary, fan2 expect value will load from segment 1 register (index bah). when vt2 temperature is below this boundary ? hysteresis, fan2 expect value will load from segment 2 register (index bbh). this byte is a 2?s complement value ranging from -128?c ~ 127?c. 8.3.2.67 vt2 boundary 2 temperature register ? index b7 bit name r/w default description
dec, 2010 v0.18p 82 F71808A 7-0 bound2tmp2 r/w 32h (50 o c) the 2 nd boundary temperature for vt2 in temperature mode. when vt2 temperature is exceed this boundary, fan2 expect value will load from segment 2 register (index bbh). when vt2 temperature is below this boundary ? hysteresis, fan2 expect value will load from segment 3 register (index bch). this byte is a 2?s complement value ranging from -128?c ~ 127?c. 8.3.2.68 vt2 boundary 3 temperature register ? index b8 bit name r/w default description 7-0 bound3tmp2 r/w 28h (40 o c) the 3 rd boundary temperature for vt2 in temperature mode. when vt2 temperature is exceed this boundary, fan2 expect value will load from segment 3 register (index bch). when vt2 temperature is below this boundary ? hysteresis, fan2 expect value will load from segment 4 register (index bdh). this byte is a 2?s complement value ranging from -128?c ~ 127?c. 8.3.2.69 vt2 boundary 4 temperature register ? index b9 bit name r/w default description 7-0 bound4tmp2 r/w 1eh (30 o c) the 4th boundary temperature for vt2 in temperature mode. when vt2 temperature is exceed this boundary, fan2 expect value will load from segment 4 register (index bdh). when vt2 temperature is below this boundary ? hysteresis, fan2 expect value will load from segment 5 register (index beh). this byte is a 2?s complement value ranging from -128?c ~ 127?c. 8.3.2.70 fan2 segment 1 speed count register ? index bah bit name r/w default description
dec, 2010 v0.18p 83 F71808A 7 - 0 sec1speed2 r /w ffh (100%) the meaning of this register is depending on the fan2_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. ex: 100% full speed: user must set this register to 0. 60% full speed: (100-60)*32/60, so user must program 21 to this reg. x% full speed: the value programming in this byte is ? (100-x)*32/x 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. 8.3.2.71 fan2 segment 2 speed count register ? index bbh bit name r/w default description 7 - 0 sec2speed2 r /w d9h (85%) the meaning of this register is depending on the fan2_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. 8.3.2.72 fan2 segment 3 speed count register ? index bch bit name r/w default description 7 - 0 sec3speed2 r /w b2h (70%) the meaning of this register is depending on the fan2_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. 8.3.2.73 fan2 segment 4 speed count register ? index bdh bit name r/w default description
dec, 2010 v0.18p 84 F71808A 7 - 0 sec4speed2 r /w 99h (60%) the meaning of this register is depending on the fan2_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. 8.3.2.74 fan2 segment 5 speed count register ? index beh bit name r/w default description 7 - 0 sec5peed2 r /w 80h (50%) the meaning of this register is depending on the fan2_mode(cr96) 2?b00: the value that set in this byte is the relative expect fan speed % of the full speed in this temperature section. 2?b01: the value that set in this byte is mean the expect pwm duty-cycle in this temperature section. 8.3.2.75 fan2 temperature mapping select register ? index bfh bit name r/w default description 7 fan2_temp_sel_dig r/w 0 this bit companying with fan2_temp_sel select the temperature source for controlling fan2. 6 reserved - - reserved 5 fan2_up_t_en r /w 0 set 1 to force fan2 to full speed if any temperature over its high limit. 4 fan2_interpolatio n_en r/w 1 set 1 will enable the interpolat ion of the fan expect table. 3 fan2_jump_high_en r/w 1 this register controls the fan2 duty movement when temperature over highest boundary. 0: the fan2 duty will increases with the slope selected by fan2_up_rate register. 1: the fan2 duty will directly jumps to the value o f sec1speed2 register. this bit only activates in duty mode.
dec, 2010 v0.18p 85 F71808A 2 fan2_jump_low_en r/w 1 this register controls the fan2 duty movement when temperature under (highest boundary ? hysteresis). 0: the fan2 duty will decreases with the slope selected by fan2_dn_rate register. 1: the fan2 duty will directly jumps to the value o f sec2speed2 register. this bit only activates in duty mode. 1 - 0 fan2_temp_sel r /w 10 this registers companying with fan2_temp_sel_dig select the temperature source for controlling fan2. the following value is comprised by {fan2_temp_sel_dig, fan2_temp_sel} 000: fan1 follows peci temperature (cr7eh) 001: fan1 follows temperature 1 (cr72h). 010: fan1 follows temperature 2 (cr74h). 011: fan1 follows temperature 3 (cr76h). 100: fan1 follows ibx/tsi cpu temperature (cr7ah) 101: fan1 follows ibx pch temperature (cr7bh). 110: fan1 follows ibx m ch temperature (cr7ch). 111: fan1 follows ibx maximum temperature (cr7dh). otherwise: reserved. 8.3.2.76 fan3 index c0h- cfh address attribute default value description c0h ro 8?h0f fan3 count reading (msb). at the mom ent of reading this register, the lsb will be latched. this will prevent from data updating when reading. to read the fan count correctly, read msb first and followed read the lsb. c1h ro 8?hff fan3 count reading (lsb). c2h reserved - reserved c3h r/w 8?h7f the value programming in this byte is duty value for pwm pin. c4h~ceh reserved - reserved 8.3.2.77 pwm configuration register ? index cfh bit name r/w default description
dec, 2010 v0.18p 86 F71808A 7 - 6 pwm_freq_sel r /w 0 pwm pin output frequency selection 00: 23.5 khz 01: 11.75 khz 10: 5.875 khz 11: 220hz 5-4 reserved - - set to select fan3 filter. (reserved for fintek only) 3-1 reserved - - reserved 0 pwm_ext_en r / w 0 0: pwm pin output duty is set by programming index c3h 1: pwm pin output duty is controlled by pin 53 (+) and p 54 (-). there are total 16 steps for external control. 8.3.2.78 tsi temperature 0 register? index e0h bit name r/w default description 7-0 tsi_temp0 r - this is the amd tsi reading if amd tsi enable. and will be highest temperatur e among cpu, mch and pch if intel temperature interface enable. the range is 0~255?c. 8.3.2.79 tsi temperature 1 register? index e1h bit name r/w default description 7-0 tsi_temp1 r - this is the high byte of intel temperature interf ace pch reading. the range is 0~255?c. 8.3.2.80 tsi temperature 2 low byte register? index e2h bit name r/w default description 7 - 0 tsi_temp2_lo r - this is the low byte of intel temperature interface cpu reading. the reading is the fraction part of cpu temperature. bit 0 indicates the error status. 0: no error. 1: error code. 8.3.2.81 tsi temperature 2 high byte register? index e3h bit name r/w default description 7-0 tsi_temp2_hi r - this is the high byte of intel te mperature interface cpu reading. the reading is the decimal part of cpu temperature. 8.3.2.82 tsi temperature 3 register? index e4h bit name r/w default description
dec, 2010 v0.18p 87 F71808A 7-0 tsi_temp3 r - this is the high byte of intel temperature interf ace mch reading. the range is 0~255?c. 8.3.2.83 smb master block count byte ? index ech bit name r/w default description 7-6 reserved - - reserved 5-0 block_cnt r/w 0 1. use the register to specify the byte count of block write protocol. (support up to 5 bytes of block write protocol). 2. smb master will save the ?block read count? here when receiving a block-read protocol. 8.3.2.84 amd tsi/intel ibex comma nd byte register ? index edh bit name r/w default description 7-0 tsi_cmd r/w 1h tsi_cmd, which is the command code for intel temperature interface block read protocol and th e data byte for amd tsi send byte protocol. 8.3.2.85 smb master status and control register ? index eeh bit name r/w default description 7 tsi_pending r/w 0 set 1 to pending auto tsi accessing. (in amd model, auto accessing will issue a send-byte followed a receive-byte; in intel model, auto accessing will issue a block read). to use the tsi_scl/tsi_sda as a smbus master, set this bit to ?1? first. 6 reserved - - reserved 5 proc_kill r/w 0 kill the current smbus transfer an d return the state machine to idle. it will set an fail status if the current transfer is not completed. 4 fail_sts r 0 this is set when proc_ki ll kill an un-completed transfer. it will be auto cleared by next smbus transfer. 3 smb_abt_err r 0 this is the arbitration lost status if a smbus command is issued. auto cleared by next smbus command. 2 smb_to_err r 0 this is the timeout status if a smbus command is issued. auto cleared by next smbus command. 1 smb_nac_err r 0 this is the nack error status if a smbus command is issued. auto cleared by next smbus command. 0 smb_ready r 1 0: a smbus transfer is in process. 1: ready for next smbus command. 8.3.2.86 smb master control register ? index efh bit name r/w default description 7 smb_start w 0 write ?1? to trigger a smbus master transfer with the protocol specified by smb_protocol. 6-4 reserved - - reserved.
dec, 2010 v0.18p 88 F71808A 3-0 smb_protocol r/w 0 select what protocol if smbus transfer is triggered. 0001b: send byte. 0010b: write byte. 0011b: write word. 0100b: process call. 0101b: block write. 0111b: quick command (write). 1001b: receive byte. 1010b: read byte. 1011b: read word. 1101b: block read. 1111b: quick command (read). otherwise: reserved. 8.4 kbc registers (ldn 0x05) 8.4.1 kbc device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 kbc_en r/w 1 0: disable kbc. 1: enable kbc. 8.4.2 base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 00h the msb of kbc command port address. the address of data port is command port address + 4; 8.4.3 base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w 60h the lsb of kbc command port address. the address of data port is command port address + 4. 8.4.4 kb irq channel select register ? index 70h bit name r/w default description 7-4 reserved - - reserved. 3-0 selkirq r/w 1h select the irq channel for keyboard interrupt. 8.4.5 mouse irq channel select register ? index 72h bit name r/w default description
dec, 2010 v0.18p 89 F71808A 7-4 reserved - - reserved. 3-0 selmirq r/w ch select the irq channel for ps/2 mouse interrupt. 8.4.6 auto swap register ? index feh (powered by vbat) bit name r/w default description 7 auto_det_en r/w 0 0: disable auto detect keyboard/mouse swap. 1: enable auto detect keyboard/mouse swap. 6-5 reserved - - reserved. 4 kb_mo_swap r/w 0 0: keyboard/mouse not swap. 1: keyboard/mouse swap. this bit is set/clear by hardware if auto_det_en is set to ?1?. users could also program this bit manually. 3 pseudo_8408_en r/w 0 set ?1? to enable auto response to kbc command. it will return 0xfa, 0xaa for 0xff command and 0xfa for other commands. this bit is used for gpio scan code function without ps/2 keyboard. 2-0 reserved - - reserved. 8.4.7 user wakeup code register ? index ffh (powered by vbat) bit name r/w default description 7-0 user_wakeup_ code r/w 29h this is user define wakeup code. default is space. 8.5 gpio registers (ldn 0x06) 8.5.1 gpirq channel select register ? index 70h bit name r/w default description 7-4 reserved - - reserved. 3-0 selgpirq r/w 0h select the irq channel for gpio interrupt. 8.5.2 gpio3 output enable register ? index c0h bit name r/w default description 7-6 reserved - - reserved. 4 gpio35_oe r/w 0 0: gpio35 is in input mode. 1: gpio35 is in output mode.
dec, 2010 v0.18p 90 F71808A 4 gpio34_oe r/w 0 0: gpio34 is in input mode. 1: gpio34 is in output mode. 3 gpio33_oe r/w 0 0: gpio33 is in input mode. 1: gpio33 is in output mode. 2 gpio32_oe r/w 0 0: gpio32 is in input mode. 1: gpio32 is in output mode. 1 gpio31_oe r/w 0 0: gpio31 is in input mode. 1: gpio31 is in output mode. 0 gpio30_oe r/w 0 0: gpio30 is in input mode. 1: gpio30 is in output mode. 8.5.3 gpio3 output data register ? index c1h bit name r/w default description 7-6 reserved - - reserved. 5 gpio35_val r/w 1 0: gpio35 outputs 0 when in output mode. 1: gpio35 outputs 1 when in output mode. 4 gpio34_val r/w 1 0: gpio34 outputs 0 when in output mode. 1: gpio34 outputs 1 when in output mode. 3 gpio33_val r/w 1 0: gpio33 outputs 0 when in output mode. 1: gpio33 outputs 1 when in output mode. 2 gpio32_val r/w 1 0: gpio32 outputs 0 when in output mode. 1: gpio32 outputs 1 when in output mode. 1 gpio31_val r/w 1 0: gpio31 outputs 0 when in output mode. 1: gpio31 outputs 1 when in output mode. 0 gpio30_val r/w 1 0: gpio30 outputs 0 when in output mode. 1: gpio30 outputs 1 when in output mode. 8.5.4 gpio3 pin status register ? index c2h bit name r/w default description 7-6 reserved - - reserved. 5 gpio35_in r - the pin status of fanin2/gpio35 4 gpio34_in r - the pin status of fanctl2/gpio34. 3 gpio33_in r - the pin status of scl/gpio33. 2 gpio32_in r - the pin status of peci/sdat/gpio32. 1 gpio31_in r - the pin status of vldt_en/gpio31 0 gpio30_in r - the pin status of vcore_en/gpio30 8.5.5 gpio3 drive enable register ? index c3h bit name r/w default description 7-6 reserved - - reserved 5 gpio35_drv_en r/w 0 0: gpio35 is open drain in output mode. 1: gpio35 is push pull in output mode.
dec, 2010 v0.18p 91 F71808A 4 gpio34_drv_en r/w 0 0: gpio34 is open drain in output mode. 1: gpio34 is push pull in output mode. 3 gpio33_drv_en r/w 0 0: gpio33 is open drain in output mode. 1: gpio33 is push pull in output mode. 2 gpio32_drv_en r/w 0 0: gpio32 is open drain in output mode. 1: gpio32 is push pull in output mode. 1 gpio31_drv_en r/w 0 0: gpio31 is open drain in output mode. 1: gpio31 is push pull in output mode. 0 gpio30_drv_en r/w 0 0: gpio30 is open drain in output mode. 1: gpio30 is push pull in output mode. 8.5.6 event pme enable register ? index c4h (* reset by lreset#) bit name r/w default description 7-5 reserved - - reserved. 4 gpio01_pme_en r/w 0* when gpio01_pme_sts is 1 and gpio01_pme_en is set to 1, a gpio pme event will be generated. 3 gpio00_pme_en r/w 0* when gpio00_pme_sts is 1 and gpio00_pme_en is set to 1, a gpio pme event will be generated. 2 gpio05_pme_en r/w 0* when gpio05_pme_sts is 1 and gpio05_pme_en is set to 1, a gpio pme event will be generated. 1 gpio31_pme_en r/w 0 when gpio31_pme_sts is 1 and gpio30_pme_en is set to 1, a gpio pme event will be generated. 0 gpio30_pme_en r/w 0 when gpio30_pme_sts is 1 and gpio30_pme_en is set to 1, a gpio pme event will be generated. 8.5.7 gpio3 input detection select register ? index c5h (*reset by lreset#) bit name r/w default description 7-5 reserved - - reserved. 4 gpio01_det_sel r/w 0 when gpio01 is in input mode, set this bit to select which input event should be detected. 0: rising edge 1: falling edge 3 gpio00_det_sel r/w 0 when gpio00 is in input mode, set this bit to select which input event should be detected. 0: rising edge 1: falling edge
dec, 2010 v0.18p 92 F71808A 2 gpio05_det_sel r/w 0* when gpio05 is in input mode, set this bit to select which input event should be detected. 0: rising edge 1: falling edge 1 gpio31_det_sel r/w 0* when gpio31 is in input mode, set this bit to select which input event should be detected. 0: rising edge 1: falling edge 0 gpio30_det_sel r/w 0* when gpio30 is in input mode, set this bit to select which input event should be detected. 0: rising edge 1: falling edge 8.5.8 gpio3 event status register ? index c6h (*reset by lreset#) bit name r/w default description 7-5 reserved - - reserved. 4 gpio01_pme_sts r/wc 0 when gpio01 is in input mode and a gpio01 input is detected, this bit will be set to 1. write a 1 to this bit will clear it to 0. 3 gpio00_pme_sts r/wc 0 when gpio00 is in input mode and a gpio00 input is detected, this bit will be set to 1. write a 1 to this bit will clear it to 0. 2 gpio05_pme_sts r/wc 0* when gpio05 is in input mode and a gpio05 input is detected, this bit will be set to 1. write a 1 to this bit will clear it to 0. 1 gpio31_pme_sts r/wc 0* when gpio31 is in input mode and a gpio31 input is detected, this bit will be set to 1. write a 1 to this bit will clear it to 0. 0 gpio30_pme_sts r/wc 0* when gpio30 is in input mode and a gpio30 input is detected, this bit will be set to 1. write a 1 to this bit will clear it to 0. 8.5.9 gpio05 kb emulation key code register ? index cbh bit name r/w default description
dec, 2010 v0.18p 93 F71808A 0 gp05_kb_code r/w 0 the make code of gp05 keyboard emulation key. the break code is gp05_kb_code + 0x80. 8.5.10 gpio31 kb emulation key code register ? index cch bit name r/w default description 0 gp31_kb_code r/w 0 the make code of gp31 keyboard emulation key. the break code is gp31_kb_code + 0x80. 8.5.11 gpio30 kb emulation key code register ? index cdh bit name r/w default description 0 gp30_kb_code r/w 0 the make code of gp30 keyboard emulation key. the break code is gp30_kb_code + 0x80. 8.5.12 kb emulation key prefix code register ? index ceh bit name r/w default description 0 pre_kb_code r/w 0xe0 the prefix code when pre_code_e n is set. two byte will send when key is pressed or released. for example, when gp30 is pressed, 0xe0 will be sent first and then gp30_kb_code is sent. 8.5.13 event kbc control register ? index cfh bit name r/w default description 7 gp_kbc_en r/w 0 set this bit to enable keyboard key emulation function. 6 pre_code_en r/w 1 0: emulation code is one byte decided by make code. 1: emulation code is two bytes with pre-fix defined in pre_code. 5 gp05_brk_sts r/w c 0 the keyboard key emulation stat us of break code by gpio05. when keyboard key emulation event occurs and the break code of this key is sent, this bit will be set to 1. gp05_brk_sts will be cleared after host reading io port 0x0060. 4 gp05_make_sts r/w c 0 the keyboard key emulation status of make code by gpio05. when keyboard key emulation event occurs and the make code of this key is sent, this bit will be set to 1. gp05_make_sts will be cleared after host reading io port 0x0060. the status will continue to occur when the key is pressed. delay time is 0.5 ~ 1sec with 50ms repeat time. 3 gp31_brk_sts r/w c 0 the keyboard key emulation stat us of break code by gpio31. when keyboard key emulation event occurs and the break code of this key is sent, this bit will be set to 1. gp31_brk_sts will be cleared after host reading io port 0x0060.
dec, 2010 v0.18p 94 F71808A 2 gp31_make_sts r/w c 0 the keyboard key emulation status of make code by gpio31. when keyboard key emulation event occurs and the make code of this key is sent, this bit will be set to 1. gp31_make_sts will be cleared after host reading io port 0x0060. the status will continue to occur when the key is pressed. delay time is 0.5 ~ 1sec with 50ms repeat time. 1 gp30_brk_sts r/w c 0 the keyboard key emulation stat us of break code by gpio30. when keyboard key emulation event occurs and the break code of this key is sent, this bit will be set to 1. gp30_brk_sts will be cleared after host reading io port 0x0060. 0 gp30_make_sts r/w c 0 the keyboard key emulation status of make code by gpio30. when keyboard key emulation event occurs and the make code of this key is sent, this bit will be set to 1. gp30_make_sts will be cleared after host reading io port 0x0060. the status will continue to occur when the key is pressed. delay time is 0.5 ~ 1sec with 50ms repeat time. 8.5.14 gpio2 output enable register ? index d0h bit name r/w default description 7 gpio27_oe r/w 0 0: gpio27 is in input mode. 1: gpio27 is in output mode. 6 gpio26_oe r/w 0 0: gpio26 is in input mode. 1: gpio26 is in output mode. 5 gpio25_oe r/w 0 0: gpio25 is in input mode. 1: gpio25 is in output mode. 4 gpio24_oe r/w 0 0: gpio24 is in input mode. 1: gpio24 is in output mode. 3 gpio23_oe r/w 0 0: gpio23 is in input mode. 1: gpio23 is in output mode. 2 gpio22_oe r/w 0 0: gpio22 is in input mode. 1: gpio22 is in output mode. 1 gpio21_oe r/w 0 0: gpio21 is in input mode. 1: gpio21 is in output mode. 0 gpio20_oe r/w 0 0: gpio20 is in input mode. 1: gpio20 is in output mode. 8.5.15 gpio2 output data register ? index d1h bit name r/w default description 7 gpio27_val r/w 0 0: gpio27 outputs 0 when in output mode. 1: gpio27 outputs 1 when in output mode. 6 gpio26_val r/w 0 0: gpio26 outputs 0 when in output mode. 1: gpio26 outputs 1 when in output mode. 5 gpio25_val r/w 0 0: gpio25 outputs 0 when in output mode. 1: gpio25 outputs 1 when in output mode.
dec, 2010 v0.18p 95 F71808A 4 gpio24_val r/w 0 0: gpio24 outputs 0 when in output mode. 1: gpio24 outputs 1 when in output mode. 3 gpio23_val r/w 0 0: gpio23 outputs 0 when in output mode. 1: gpio23 outputs 1 when in output mode. 2 gpio22_val r/w 0 0: gpio22 outputs 0 when in output mode. 1: gpio22 outputs 1 when in output mode. 1 gpio21_val r/w 0 0: gpio21 outputs 0 when in output mode. 1: gpio21 outputs 1 when in output mode. 0 gpio20_val r/w 0 0: gpio20 outputs 0 when in output mode. 1: gpio20 outputs 1 when in output mode. 8.5.16 gpio2 pin status register ? index d2h bit name r/w default description 7 gpio27_in r - the pin status of psin#/gpio27. 6 gpio26_in r - the pin status of resetcon#/wdrst#/gpio26. 5 gpio25_in r - the pin status of gpio25/ledvcc. 4 gpio24_in r - the pin status of gpio24/ledvsb. 3 gpio23_in r - the pin status of 5va_pwok# / gpio23 / wdtrst# / fanin3. 2 gpio22_in r - the pin status of gpio22/pwm/erp_ctrl1#. 1 gpio21_in r - the pin status of gpio21/fanin3/ovt#. 0 gpio20_in r - the pin status of gpio20/pme#. 8.5.17 gpio2 drive enable register ? index d3h bit name r/w default description 7 gpio27_drv_en r/w 0 0: gpio27 is open drain in output mode. 1: gpio27 is push pull in output mode. 6 gpio26_drv_en r/w 0 0: gpio26 is open drain in output mode. 1: gpio26 is push pull in output mode. 5 gpio25_drv_en r/w 0 0: gpio25 is open drain in output mode. 1: gpio25 is push pull in output mode. 4 gpio24_drv_en r/w 0 0: gpio24 is open drain in output mode. 1: gpio24 is push pull in output mode. 3 gpio23_drv_en r/w 0 gpio23 is open drain in output mode. 2 gpio22_drv_en r/w 0 0: gpio22 is open drain in output mode. 1: gpio22 is push pull in output mode. 1 gpio21_drv_en r/w 0 0: gpio21 is open drain in output mode. 1: gpio21 is push pull in output mode. 0 gpio20_drv_en r/w 0 0: gpio20 is open drain in output mode. 1: gpio20 is push pull in output mode. 8.5.18 gpio2 pme enable register ? index d4h bit name r/w default description 7-6 reserved - - reserved.
dec, 2010 v0.18p 96 F71808A 5 gpio25_pme_en r/w 0 when gpio25_pme_sts is 1 and gpio25_pme_en is set to 1, a gpio pme event will be generated. 4 gpio24_pme_en r/w 0 when gpio24_pme_sts is 1 and gpio24_pme_en is set to 1, a gpio pme event will be generated. 3 gpio23_pme_en r/w 0 when gpio23_pme_sts is 1 and gpio23_pme_en is set to 1, a gpio pme event will be generated. 2 gpio22_pme_en r/w 0 when gpio22_pme_sts is 1 and gpio22_pme_en is set to 1, a gpio pme event will be generated. 1-0 reserved - - reserved. 8.5.19 gpio2 input detection select register ? index d5h bit name r/w default description 7-6 reserved - - reserved. 5 gpio25_det_sel r/w 0 when gpio25 is in input mode, set this bit to select which input event should be detected. 0: rising edge 1: falling edge 4 gpio24_det_sel r/w 0 when gpio24 is in input mode, set this bit to select which input event should be detected. 0: rising edge 1: falling edge 3 gpio23_det_sel r/w 0 when gpio23 is in input mode, set this bit to select which input event should be detected. 0: rising edge 1: falling edge 2 gpio22_det_sel r/w 0 when gpio22 is in input mode, set this bit to select which input event should be detected. 0: rising edge 1: falling edge 1-0 reserved - - reserved. 8.5.20 gpio2 event status register ? index d6h bit name r/w default description 7-6 reserved - - reserved. 5 gpio25_pme_st s r/w c 0 when gpio25 is in input mode and a gpio25 input is detected, this bit will be set to 1. write a 1 to this bit will clear it to 0. 4 gpio24_pme_st s r/w c 0 when gpio24 is in input mode and a gpio24 input is detected, this bit will be set to 1. write a 1 to this bit will clear it to 0.
dec, 2010 v0.18p 97 F71808A 3 gpio23_pme_st s r/w c 0 when gpio23 is in input mode and a gpio23 input is detected, this bit will be set to 1. write a 1 to this bit will clear it to 0. 2 gpio22_pme_st s r/w c 0 when gpio22 is in input mode and a gpio22 input is detected, this bit will be set to 1. write a 1 to this bit will clear it to 0. 1-0 reserved - - reserved. 8.5.21 gpio2 output mode status register ? index d7h bit name r/w default description 7-6 gpio25_mode r/w 0 gpio25_mode is used to select the output mode of gpio25: 00: high level mode 01: inverted level mode 10: high pulse mode 11: low pulse mode 5-4 gpio24_mode r/w 0 gpio24_mode is used to select the output mode of gpio24: 00: level mode 01: inverted level mode 10: high pulse mode 11: low pulse mode 3-2 gpio23_mode r/w 0 gpio23_mode is used to select the output mode of gpio23: 00: level mode 01: inverted level mode 10: high pulse mode 11: low pulse mode 1-0 gpio22_mode r/w 0 gpio22_mode is used to select the output mode of gpio22: 00: level mode 01: inverted level mode 10: high pulse mode 11: low pulse mode 8.5.22 gpio2 pulse width of pulse mode status register ? index d8h bit name r/w default description 7-6 gpio25_pw_sel r/w 0 gpio25_pw_sel is used to select the output pulse width of pulse mode: 00: 500us 01: 1ms 10: 20ms 11: 100ms 5-4 gpio24_pw_sel r/w 0 gpio24_pw_sel is used to select the output pulse width of pulse mode: 00: 500us 01: 1ms 10: 20ms 11: 100ms
dec, 2010 v0.18p 98 F71808A 3-2 gpio23_pw_sel r/w 0 gpio23_pw_sel is used to select the output pulse width of pulse mode: 00: 500us 01: 1ms 10: 20ms 11: 100ms 1-0 gpio22_pw_sel r/w 0 gpio22_pw_sel is used to select the output pulse width of pulse mode: 00: 500us 01: 1ms 10: 20ms 11: 100ms 8.5.23 gpio1 output enable register ? index e0h bit name r/w default description 7-5 reserved - - reserved. 4 gpio14_oe r/w 0 0: gpio14 is in input mode. 1: gpio14 is in output mode. 3 gpio13_oe r/w 0 0: gpio13 is in input mode. 1: gpio13 is in output mode. 2 gpio12_oe r/w 0 0: gpio12 is in input mode. 1: gpio12 is in output mode. 1 gpio11_oe r/w 0 0: gpio11 is in input mode. 1: gpio11 is in output mode. 0 gpio10_oe r/w 0 0: gpio10 is in input mode. 1: gpio10 is in output mode. 8.5.24 gpio1 output data register ? index e1h bit name r/w default description 7-5 reserved - - reserved. 4 gpio14_val r/w 1 0: gpio14 outputs 0 when in output mode. 1: gpio14 outputs 1 when in output mode. 3 gpio13_val r/w 1 0: gpio13 outputs 0 when in output mode. 1: gpio13 outputs 1 when in output mode. 2 gpio12_val r/w 1 0: gpio12 outputs 0 when in output mode. 1: gpio12 outputs 1 when in output mode. 1 gpio11_val r/w 1 0: gpio11 outputs 0 when in output mode. 1: gpio11 outputs 1 when in output mode. 0 gpio10_val r/w 1 0: gpio10 outputs 0 when in output mode. 1: gpio10 outputs 1 when in output mode. 8.5.25 gpio1 pin status register ? index e2h bit name r/w default description 7-5 reserved - - reserved.
dec, 2010 v0.18p 99 F71808A 4 gpio14_in r - the pin status of psout#/gpio14. 3 gpio13_in r - the pin status of sus_warn#/mclk/gpio13/cirwb#. 2 gpio12_in r - the pin status of sus_ack#/mdat/gpio12. 1 gpio11_in r - the pin status of kclk/gpio11. 0 gpio10_in r - the pin status of kdat/gpio10. 8.5.26 gpio1 drive enable register ? index e3h bit name r/w default description 7-5 reserved - - reserved. 4 gpio14_drv_en r/w 0 0: gpio14 is open drain in output mode. 1: gpio14 is push pull in output mode. 3 gpio13_drv_en r/w 0 0: gpio13 is open drain in output mode. 1: gpio13 is push pull in output mode. 2 gpio12_drv_en r/w 0 0: gpio12 is open drain in output mode. 1: gpio12 is push pull in output mode. 1 gpio11_drv_en r/w 0 0: gpio11 is open drain in output mode. 1: gpio11 is push pull in output mode. 0 gpio10_drv_en r/w 0 0: gpio10 is open drain in output mode. 1: gpio10 is push pull in output mode. 8.5.27 gpio0 output enable register ? index f0h bit name r/w default description 7 gpio07_oe r/w 0 0: gpio07 is in input mode. 1: gpio07 is in output mode. 6 gpio06_oe r/w 0 0: gpio06 is in input mode. 1: gpio06 is in output mode. 5 gpio05_oe r/w 0 0: gpio05 is in input mode. 1: gpio05 is in output mode. 4 gpio04_oe r/w 0 0: gpio04 is in input mode. 1: gpio04 is in output mode. 3 gpio03_oe r/w 0 0: gpio03 is in input mode. 1: gpio03 is in output mode. 2 gpio02_oe r/w 0 0: gpio02 is in input mode. 1: gpio02 is in output mode. 1 gpio01_oe r/w 0 0: gpio01 is in input mode. 1: gpio01 is in output mode. 0 gpio00_oe r/w 0 0: gpio00 is in input mode. 1: gpio00 is in output mode. 8.5.28 gpio0 output data register ? index f1h bit name r/w default description 7 gpio07_val r/w 1 0: gpio07 outputs 0 when in output mode. 1: gpio07 outputs 1 when in output mode.
dec, 2010 v0.18p 100 F71808A 6 gpio06_val r/w 1 0: gpio06 outputs 0 when in output mode. 1: gpio06 outputs 1 when in output mode. 5 gpio05_val r/w 1 0: gpio05 outputs 0 when in output mode. 1: gpio05 outputs 1 when in output mode. 4 gpio04_val r/w 1 0: gpio04 outputs 0 when in output mode. 1: gpio04 outputs 1 when in output mode. 3 gpio03_val r/w 1 0: gpio03 outputs 0 when in output mode. 1: gpio03 outputs 1 when in output mode. 2 gpio02_val r/w 1 0: gpio02 outputs 0 when in output mode. 1: gpio02 outputs 1 when in output mode. 1 gpio01_val r/w 1 0: gpio01 outputs 0 when in output mode. 1: gpio01 outputs 1 when in output mode. 0 gpio00_val r/w 1 0: gpio00 outputs 0 when in output mode. 1: gpio00 outputs 1 when in output mode. 8.5.29 gpio pin status register ? index f2h bit name r/w default description 7 gpio07_in r - the pin status of gpio07/cirwb#/gpio07. 6 gpio06_in r - the pin status of gpio06/ sout/2e_4e. 5 gpio05_in r - the pin status of gpio05/beep/dsr#. 4 gpio04_in r - the pin status of gpio04/pwm/rts#. 3 gpio03_in r - the pin status of gpio03/cir_tx/dtr#. 2 gpio02_in r - the pin status of gpio02/cir_led/cts#. 1 gpio01_in r - the pin status of gpio01/ovt#/ri#. 0 gpio00_in r - the pin status of gpio00/sda/dcd#. 8.5.30 gpio drive enable register ? index f3h bit name r/w default description 7 gpio07_drv_en r/w 0 0: gpio07 is open drain in output mode. 1: gpio07 is push pull in output mode. 6 gpio06_drv_en r/w 0 0: gpio06 is open drain in output mode. 1: gpio06 is push pull in output mode. 5 gpio05_drv_en r/w 0 0: gpio05 is open drain in output mode. 1: gpio05 is push pull in output mode. 4 gpio04_drv_en r/w 0 0: gpio04 is open drain in output mode. 1: gpio04 is push pull in output mode. 3 gpio03_drv_en r/w 0 0: gpio03 is open drain in output mode. 1: gpio03 is push pull in output mode. 2 gpio02_drv_en r/w 0 0: gpio02 is open drain in output mode. 1: gpio02 is push pull in output mode. 1 gpio01_drv_en r/w 0 0: gpio01 is open drain in output mode. 1: gpio01 is push pull in output mode. 0 gpio00_drv_en r/w 0 0: gpio00 is open drain in output mode. 1: gpio00 is push pull in output mode.
dec, 2010 v0.18p 101 F71808A 8.6 wdt registers (ldn 0x07) configuration registers 8.6.1 wdt enable register ? index 30h bit name r/w default description 7-1 reserved - 0 reserved 0 wdt_en r/w 0 0: disable watch dog timer 1: enable watch dog timer 8.6.2 base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 00h the m sb of wdt base address. 8.6.3 base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w 00h the l sb of wdt base address. device registers 8.6.4 configuration register ? index f0h (offset + 00h) bit name r/w default description 7 wdout_en r/w 0 if this bit is set to 1 and watchdog timeout event occurs, wdtrst# output is enabled. 6-4 reserved - - reserved 3-0 reserved - - reserved 8.6.5 register ? index f2h~f4h bit name r/w default description 7-0 reserved - - reserved 8.6.6 watchdog timer configuration register 1 ? index 05h bit name r/w default description 7 reserved - - reserved 6 wdtmout_sts r/w 0 if watchdog timeout event occurs, this bit will be set to 1. write a 1 to this bit will clear it to 0. 5 wd_en r/w 0 if this bit is set to 1, the counting of watchdog time is enabled. 4 wd_pulse r/w 0 select output mode (0: level, 1: pulse) of rstout# by setting this bit.
dec, 2010 v0.18p 102 F71808A 3 wd_unit r/w 0 select time unit (0: 1sec, 1: 60 sec) of watchdog timer by setting this bit. 2 wd_hactive r/w 0 select output polarity of rstout# (1: high active, 0: low active) by setting this bit. 1:0 wd_pswidth r/w 0 select output pulse width of rstout# 0: 1 ms 1: 25 ms 2: 125 ms 3: 5 sec 8.6.7 watchdog timer configuration register 2 ? index 06h bit name r/w default description 7:0 wd_time r/w ah time of watchdog timer 8.6.8 wdt pme register ? index 07h bit name r/w default description 7 wdt_pme r 0 wdt pme real time status. 6 wdt_pme_en r/w 0 0: disable wdt pme. 1: enable wdt pme. 5 wdt_pme_st r/w 0 0: no wdt pme occurred. 1: wdt pme occurred. the wdt pme is occurred one unit before wdt timeout. 4-0 reserved - - reserved 8.7 cir registers (ldn 0x08) configuration registers 8.7.1 cir enable register ? index 30h bit name r/w default description 7-1 reserved - 0 reserved 0 cir_en r/w 0 0: disable cir 1: enable cir 8.7.2 base address high register ? index 60h bit name r/w default description 7-0 base_addr_hi r/w 00h the m sb of cir base address. 8.7.3 base address low register ? index 61h bit name r/w default description 7-0 base_addr_lo r/w 00h the lsb of cir base address.
dec, 2010 v0.18p 103 F71808A 8.7.4 cirirq channel select register ? index 70h bit name r/w default description 7-4 reserved - - reserved. 3-0 selcirirq r/w 0h select the irq channel for cir interrupt. device register 8.7.5 cir status register ? index 00h bit name r/w default description 7 cir_irq_en r/w 0 cir irq function enable 6-4 reserved r 0 reserved 3 tx_finish r/w 0 cir transmittion finish status. write 1 clear. 2 tx_underrun r/w 0 cir transmitttion underrun status. write 1 clear. 1 rx_timeout r/w 0 cir receiver timeout status. write 1 clear. 0 rx_receive r/w 0 cir receiver rece ives data status. write 1 clear. 8.7.6 cir rx data register ? index 01h bit name r/w default description 7-0 rx_data r - cir received data is read from here. 8.7.7 cir tx control register ? index 02h bit name r/w default description 7 tx_start r/w 0 set 1 to start cir tx transmittion and will be auto cleared if transmittion is finished. 6 tx_end r/w 0 set 1 to indicate that all tx data has been written to cir tx fifo. 5-0 reserved - - reserved 8.7.8 cir tx data register ? index 03h bit name r/w default description 7-0 tx_data r/w - the transmittion data should be written to tx_data. 8.7.9 cir control register ? index 04h bit name r/w default description 7-0 cir_cmd r/w 0 host writes command to cir.
dec, 2010 v0.18p 104 F71808A 8.8 pme, acpi, power saving registers (ldn 0x0a) configuration register 8.8.1 device enable register ? index 30h bit name r/w default description 7-1 reserved - - reserved 0 pme_en r/w 0 0: disable pme. 1: enable pme. 8.8.2 eup enable register ? index e0h bit name r/w default description 7 eup_en r/w 0 0 : disable eup function 1: enable eup function 6-5 reserved - 0 reserved. 4 vsb_ctrl_1_en r/w 1 vsb_ctrl_1 enable. 0: disable vsb_ctrl_1 function. 1: function of pin 20 is vsb_ctrl_1 3-2 reserved - - reserved 1 event_pme_en r/w 0 event_in# pme event enable. 0: disable event_in# pme event. 1: enable event_in# pme event 0 event_psout_en r/w 0 event_in# psout event enable. 0: disable event_in# psout event. 1: enable event_in# psout event 8.8.3 eup control register ? index e1h bit name r/w default description 7-6 boot_mode r/w 11 write these two bits to select boot mode for always off/ always on/ keep last state. 00:default always off 11:support always on and keep last state 10:reserved 01:reserved 5 s3 _ctrl_1_dis r/w 0 if clear to ?0? ctrl_1 will output low when enter deep s3 state. else if set to ?1? ctrl_1 will output high when enter deep s3 state. 4 s3 _ctrl_0_dis r/w 0 if clear to ?0? ctrl_0 will output low when enter deep s3 state. else if set to ?1? ctrl_0 will output high when enter deep s3 state. 3 s5 _ctrl_1_dis r/w 1 if clear to ?0? ctrl_1 will output low when s5 state. else if set to ?1? ctrl_1 will output high when s5 state. 2 s5 _ctrl_0_dis r/w 1 if clear to ?0? ctrl_0 will output low when s5 state. else if set to ?1? ctrl_0 will output high when s5 state. 1 ac_ ctrl_1_dis r/w 0 if clear to ?0? ctrl_1 will output low w hen after ac lost. else if set to ?1? ctrl_1 will output high when after ac lost.
dec, 2010 v0.18p 105 F71808A 0 ac_ ctrl_0_dis r/w 0 if clear to ?0? ctrl_0 will output low w hen after ac lost. else if set to ?1? ctrl_0 will output high when after ac lost. 8.8.4 eup control register ? index e2h bit name r/w default description 7 ac_lost r/wc - set 1 if ac lost, and write 1 to clear. 6 reserved r/w 0 reserved 5 vsb_ctrl_en[1] r/w 1?b0 0: disable eup_ctrl2 assert rsmrst low 1: enable eup_ctrl2 assert rsmrst low 4 vsb_ctrl_en[0] r/w 1?b0 0: disable eup_ctrl1 assert rsmrst low 1: enable eup_ctrl1 assert rsmrst low 3 s5_det_s5# r/w 1 device into s5 state will check s5# signal and vcc_in pin status, but when user clear this bit to 0. devi ce into s5 state will not check s5# become low. 2 s5_det_vcc r/w 1 device into s5 state will check s5# signal and vcc_in pin status, but when user clear this bit to 0. device into s5 state will not check vcc_in become low. 1 rsmrst_det_5v_n r/w 0 device detects vsb5v power ok (4.4v) and vsb3v_in become high, and after 60ms de-bounce time rsmrst will become high. but when user set this bit to 1. rsmrst will not check vsb5v power ok. 0 reserved - - reserved. 8.8.5 eup psin deb-register ? index e3h bit name r/w default description .7-0 ps_deb_time r/w 0x13 ps_in pin input de-bounce time default is 20msec 8.8.6 eup rsmrst deb-register ? index e4h bit name r/w default description 7-0 rsmrst_deb_tim e r/w 0x09 rsmrst internal de-bounce time default is 10msec 8.8.7 eup psout deb-register ? index e5h bit name r/w default description 7-0 ps_out_pulse_w r/w 0xc7 ps_out_out output pulse width default is 200msec low pulse 8.8.8 eup pson deb-register ? index e6h bit name r/w default description 7-0 ps_on_deb_time r/w 0x09 pson_in pin input de-bounce time default is 10msec 8.8.9 eup s5 deb-register ? index e7h bit name r/w default description
dec, 2010 v0.18p 106 F71808A 7-0 s5_del_time r/w 0x63 delay time for s5 to deep s5 state. the unit of this byte is 64ms. default is 6.4sec 8.8.10 eup wakeup event enable register ? index e8h bit name r/w default description 7 reserved - - reserved. 6 cir_wakeup_en r/w 0 enable cir pme event to wakeup. 5 ri_wakeup_en r/w 0 enable ri# pme event to wakeup. 4 reserved - - reserved. 3 gp_wakeup_en r/w 0 enable gpio pme event to wakeup. 2 tmout_wakeup_en r/w 0 enable eup watchdog timer timeout event to wakeup. see index edh and eeh. 1 mo_wakeup_en r/w 0 enable mouse pme event to wakeup. 0 kb_wakeup_en r/w 0 enable ke yboard pme event to wakeup. 8.8.11 eup s3 delay register ? index e9h bit name r/w default description 7-0 s3_del_time r/w 0x0f delay time for s3 to deep s3 state. the unit of this byte is 64ms. default is 1.024sec 8.8.12 eup wakeup event enable register 2 ? index ech bit name r/w default description 7 pin31_waekup_en r/w 0 enable falling edge of pin 31 to trigger a wakeup event. 6 pin27_waekup_en r/w 0 enable falling edge of pin 27 to trigger a wakeup event. 5 pin23_waekup_en r/w 0 enable falling edge of pin 23 to trigger a wakeup event. 4 pin22_waekup_en r/w 0 enable falling edge of pin 22 to trigger a wakeup event. 3 pin21_waekup_en r/w 0 enable falling edge of pin 21 to trigger a wakeup event. 2 pin20_waekup_en r/w 0 enable falling edge of pin 20 to trigger a wakeup event. 1 pin19_waekup_en r/w 0 enable falling edge of pin 19 to trigger a wakeup event. 0 pin18_waekup_en r/w 0 enable falling edge of pin 18 to trigger a wakeup event. 8.8.13 eup watchdog control register ? index edh bit name r/w default description 7-6 eup_mode r/w 00 eup mode select. 00: fintek g3? mode. erp_ctrl# is controlled with fintek mechanism. 01: intel dsw + fintek g3?. 10: reserved. 11: intel dsw. 5 dpwrok_ctrl1_en r/w 0 dpwrok will follow erp_ctrl1# if this bit is set. 4 wd_tmout r/wc 0 eup watchdog timer timeout status. write 1 to clear. 3-2 revered - - reserved. 1 wd_unit r/w 0 0: unit of wd_time is 1 sec. 1: unit of wd_time is 1 minute. 0 wd_en r/w 0 enable eup watchdog timer.
dec, 2010 v0.18p 107 F71808A 8.8.14 eup watchdog time register ? index eeh bit name r/w default description 7-0 wd_time r/w 0 eup watchdog timer count time register. start to count down when wd_en is set. when reaching 0, wd_en will auto clear and wd_tmout is set. a wakeup event will assert if enabled. 8.8.15 pme event enable register 1 ? index f0h bit name r/w default description 7 wdt_pme_en r/w 0 wdt pme event enable. 0: disable wdt pme event. 1: enable wdt pme event. 6 mo_pme_en r/w 0 mouse pme event enable. 0: disable mouse pme event. 1: enable mouse pme event. 5 kb_pme_en r/w 0 keyboard pme event enable. 0: disable keyboard pme event. 1: enable keyboard pme event. 4 hm_pme_en r/w 0 hardware monitor pme event enable. 0: disable hardware monitor pme event. 1: enable hardware monitor pme event. 3-2 reserved - - reserved 1 ur_pme_en r/w 0 uart pme event enable. 0: disable uart pme event. 1: enable uart pme event. 0 reserved - - reserved 8.8.16 pme event enable register 2 ? index f1h bit name r/w default description 7 wdt_pme_st r/w c - wdt pme event status. 0: wdt has no pme event. 1: wdt has a pme event to assert. write 1 to clear to be ready for next pme event. 6 mo_pme_st r/w c - mouse pme event status. 0: mouse has no pme event. 1: mouse has a pme event to assert. write 1 to clear to be ready for next pme event. 5 kb_pme_st r/w c - keyboard pme event status. 0: keyboard has no pme event. 1: keyboard has a pme event to assert. write 1 to clear to be ready for next pme event. 4 hm_pme_st r/w c - hardware monitor pme event status. 0: hardware monitor has no pme event. 1: hardware monitor has a pme event to assert. write 1 to clear to be ready for next pme event. 3-2 reserved - - reserved
dec, 2010 v0.18p 108 F71808A 1 ur_pme_st r/w - uart pme event status. 0: uart has no pme event. 1: uart has a pme event to assert. write 1 to clear to be ready for next pme event. 0 reserved - - reserved 8.8.17 pme event status register ? index f2h bit name r/w default description 7-5 reserved - - reserved 4 cir_pme_en r/w 0 cir pme event enable. 0: disable cir pme event. 1: enable cir pme event. 3-2 reserved - - reserved 1 ri_pme_en r/w 0 ri# pme event enable. 0: disable ri# pme event. 1: enable ri# pme event. 0 gp_pme_en r/w 0 gpio pme event enable. 0: disable gpio pme event. 1: enable gpio pme event. 8.8.18 pme event status register ? index f3h bit name r/w default description 7-5 reserved - - reserved 4 cir_pme_st r/w - cir pme event status. 0: cir has no pme event. 1: cir has a pme event to assert. write 1 to clear to be ready for next pme event. 3 eup_pme_st r/w - eup pme event status. 0: eup has no pme event. 1: eup has a pme event to asser t. write 1 to clear to be ready for next pme event. 2 reserved - - reserved 1 ri_pme_st r/w - ri# pme event status. 0: ri# has no pme event. 1: ri# has a pme event to assert. write 1 to clear to be ready for next pme event. 0 gp_pme_st r/w - gpio pme event status. 0: gpio has no pme event. 1: gpio has a pme event to assert. write 1 to clear to be ready for next pme event. 8.8.19 keep last state select register ? index f4h bit name r/w default description 7 reserved r/w 0 reserved 6 en_cirwakeup r/w 0 set one to enable ci r wakeup event assert ed via pwsout#.
dec, 2010 v0.18p 109 F71808A 5 en_gpwakeup r/w 0 set one to enable gpio wakeup event asserted via pwsout#. 4 en_kbwakeup r/w 0 set one to enable keyboard wakeup event asserted via pwsout#. 3 en_mowakeup r/w 0 set one to enable mouse wakeup event asserted via pwsout#. 2-1 pwrctrl r/w 11 the acpi control the pson_n to always on or always off or keep last state 00 : keep last state 10 : always on 01 : bypass mode. 11: always off 0 vsb_pwr_loss r/w 0 when vsb 3v comes, it will set to 1, and write 1 to clear it 8.8.20 vddok delay register ? index f5h bit name r/w default description 7-6 pwrok_delay r/w 0 the additional pwrok delay. 00: no delay 01: 100ms. 10: 200ms 11: 400ms. 5 rstcon_en r/w 1 0: resetcon# will assert via pwrok. 1: resetcon# will assert via resetout1# and resetout2#. 4-3 vdd_delay r/w 11 the pwrok delay timing from vdd3vok by followed setting 00 : 100ms 01 : 200ms 10 : 300ms 11 : 400ms 2-0 reserved - - reserved. 8.8.21 pcirst control register ? index f6h bit name r/w default description 7 s3_sel r/w 0 select the kbc s3 state. 0: enter s3 state when internal vdd3vok signal de-asserted. 1: enter s3 state when s3# is low or the ts3 register is set to 1. 6 pson_del_en r/w 0 0: pson# is the inverted of s3# signal. 1: pson# will sink low only if the time after the last turn-off elapse at least 4 seconds. 5-2 reserved - - reserved. 1 resetout2_gat e r/w 1 write ?0? to this bit will force resetout2# to sink low. 0 resetout1_gat e r/w 1 write ?0? to this bit will force resetout1# to sink low. 8.8.22 power sequence control register ? index f7h bit name r/w default description 7-4 reserved r/w 0 dummy register.
dec, 2010 v0.18p 110 F71808A 3 wdt_pwrok_en r/w 0 0: disable wdt assert to pwrok pin. 1: enable wdt assert to pwrok pin. 2 pwrok_250ms w 0 write ?1? to generate a 250ms low pulse from pwrok pin. 1 s 3 _gate_tri r/w 0 0: 3vsbsw# sinks low in s5 state. 1: 3vsbsw# is driving high in s5 state. 0 reserved - - reserved. 8.8.23 led vcc mode select register ? index f8h bit name r/w default description 7 led_vcc_inv_di s r/w 0 invert led_vcc clock output. 6 led_vcc_ds3 r/w 0 enable led_vcc deep s3 mode. led_vcc will output 0.25hz cl ock with 75% duty when enter deep s3 state. 5-4 led_vcc_s5_mo de r/w 0 select led_vcc mode in s5 state. the mode is controlled by {led_vcc_s5_add, led_vcc_s5_mode} 000: sink low. 001: tri-state. 010: 0.5hz clock. 011: 1hz clock. 100: 0.125hz clock with 50% duty. 101: 0.25hz clock with 50% duty. 110: 0.125hz clock with 75% duty. 111: 0.25hz clock with 75% duty. 3-2 led_vcc_s3_mo de r/w 0 select led_vcc mode in s3 state. the mode is controlled by {led_vcc_s3_add, led_vcc_s3_mode} 000: sink low. 001: tri-state. 010: 0.5hz clock. 011: 1hz clock. 100: 0.125hz clock with 50% duty. 101: 0.25hz clock with 50% duty. 110: 0.125hz clock with 75% duty. 111: 0.25hz clock with 75% duty. 1-0 led_vcc_s0_mo de r/w 0 select led_vcc mode in s0 state. the mode is controlled by {led_vcc_s0_add, led_vcc_s0_mode} 000: sink low. 001: tri-state. 010: 0.5hz clock. 011: 1hz clock. 100: 0.125hz clock with 50% duty. 101: 0.25hz clock with 50% duty. 110: 0.125hz clock with 75% duty. 111: 0.25hz clock with 75% duty.
dec, 2010 v0.18p 111 F71808A 8.8.24 led vsb mode select register ? index f9h bit name r/w default description 7 reserved - - reserved 6 led_vsb_ds3 r/w 0 enable led_vsb deep s3 mode. led_vsb will output 0.25hz cl ock with 75% duty when enter deep s3 state. 5-4 led_vsb_s5_mo de r/w 0 select led_vsb mode in s5 state. the mode is controlled by {led_vsb_s5_add, led_vsb_s5_mode} 000: sink low. 001: tri-state. 010: 0.5hz clock. 011: 1hz clock. 100: 0.125hz clock with 50% duty. 101: 0.25hz clock with 50% duty. 110: 0.125hz clock with 75% duty. 111: 0.25hz clock with 75% duty. 3-2 led_vsb_s3_mo de r/w 0 select led_vsb mode in s3 state. the mode is controlled by {led_vsb_s3_add, led_vsb_s3_mode} 000: sink low. 001: tri-state. 010: 0.5hz clock. 011: 1hz clock. 100: 0.125hz clock with 50% duty. 101: 0.25hz clock with 50% duty. 110: 0.125hz clock with 75% duty. 111: 0.25hz clock with 75% duty. 1-0 led_vsb_s0_mo de r/w 0 select led_vsb mode in s0 state. the mode is controlled by {led_vsb_s0_add, led_vsb_s0_mode} 000: sink low. 001: tri-state. 010: 0.5hz clock. 011: 1hz clock. 100: 0.125hz clock with 50% duty. 101: 0.25hz clock with 50% duty. 110: 0.125hz clock with 75% duty. 111: 0.25hz clock with 75% duty. 8.8.25 led mode select add register ? index fah bit name r/w default description 7 reserved - - reserved
dec, 2010 v0.18p 112 F71808A 6 led_vsb_s5_ad d r/w 0 select led_vsb mode in s5 state. the mode is controlled by {led_vsb_s5_add, led_vsb_s5_mode} 000: sink low. 001: tri-state. 010: 0.5hz clock. 011: 1hz clock. 100: 0.125hz clock with 50% duty. 101: 0.25hz clock with 50% duty. 110: 0.125hz clock with 75% duty. 111: 0.25hz clock with 75% duty. 5 led_vsb_s3_ad d r/w 0 select led_vsb mode in s3 state. the mode is controlled by {led_vsb_s3_add, led_vsb_s3_mode} 000: sink low. 001: tri-state. 010: 0.5hz clock. 011: 1hz clock. 100: 0.125hz clock with 50% duty. 101: 0.25hz clock with 50% duty. 110: 0.125hz clock with 75% duty. 111: 0.25hz clock with 75% duty. 4 led_vsb_s0_ad d r/w 0 select led_vsb mode in s0 state. the mode is controlled by {led_vsb_s0_add, led_vsb_s0_mode} 000: sink low. 001: tri-state. 010: 0.5hz clock. 011: 1hz clock. 100: 0.125hz clock with 50% duty. 101: 0.25hz clock with 50% duty. 110: 0.125hz clock with 75% duty. 111: 0.25hz clock with 75% duty. 3 reserved - - reserved 2 led_vcc_s3_mo de r/w 0 select led_vcc mode in s5 state. the mode is controlled by {led_vcc_s5_add, led_vcc_s5_mode} 000: sink low. 001: tri-state. 010: 0.5hz clock. 011: 1hz clock. 100: 0.125hz clock with 50% duty. 101: 0.25hz clock with 50% duty. 110: 0.125hz clock with 75% duty. 111: 0.25hz clock with 75% duty.
dec, 2010 v0.18p 113 F71808A 1 led_vcc_s3_mo de r/w 0 select led_vcc mode in s3 state. the mode is controlled by {led_vcc_s3_add, led_vcc_s3_mode} 000: sink low. 001: tri-state. 010: 0.5hz clock. 011: 1hz clock. 100: 0.125hz clock with 50% duty. 101: 0.25hz clock with 50% duty. 110: 0.125hz clock with 75% duty. 111: 0.25hz clock with 75% duty. 0 led_vcc_s0_mo de r/w 0 select led_vcc mode in s0 state. the mode is controlled by {led_vcc_s0_add, led_vcc_s0_mode} 000: sink low. 001: tri-state. 010: 0.5hz clock. 011: 1hz clock. 100: 0.125hz clock with 50% duty. 101: 0.25hz clock with 50% duty. 110: 0.125hz clock with 75% duty. 111: 0.25hz clock with 75% duty. 8.8.26 intel dsw delay select register ? index fch bit name r/w default description 7-4 reserved r/w - reserved 3-0 dsw_delay r/w 7h this is the delay time for sus_ack# and sus_warn#. time unit is 0.5s. 8.8.27 ri de-bounce select register ? index feh bit name r/w default description 7-2 reserved - - reserved 1-0 ri_db_sel r/w 0 select ri de-bounce time. 00: reserved. 01: 200us. 10: 2ms. 11: 20ms.
dec, 2010 v0.18p 114 F71808A 9. electrical characteristics 9.1 absolute maximum ratings parameter rating unit power supply voltage -0.5 to 5.5 v input voltage -0.5 to vdd+0.5 v operating temperature 0 to +70 c storage temperature -55 to 150 c note: exposure to conditions beyond those listed u nder absolute maximum ratings may adversely affect the life and reliability of the device 9.2 dc characteristics (ta = 0 c to 70 c, vdd = 3.3v 10%, vss = 0v) (note) parameter conditons min typ max unit temperature error, remote diode 60 o c < t d < 145 o c, vcc = 3.0v to 3.6v 0 o c dec, 2010 v0.18p 115 F71808A input high threshold voltage vt+ 2.0 v vdd = 3.3 v output low current iol -12 -9 ma vol = 0.4 v output high current ioh +9 +12 ma voh = 2.4v input high leakage ilih +1 a vin = vdd input low leakage ilil -1 a vin = 0v i/o 12t - ttl level bi-directional pin, output pin with 12ma source-sink capability. input low threshold voltage vt- 0.6 v vdd = 3.3 v input high threshold voltage vt+ 0.9 v vdd = 3.3 v output high current ioh +9 +12 ma voh = 2.4v input high leakage ilih +1 a vin = 1.2v input low leakage ilil -1 a vin = 0v in ts - ttl level input pin with schmitt trigger input low voltage vil 0.8 v input high voltage vih 2.0 v input high leakage ilih +1 a vin = vdd input low leakage ilil -1 a vin = 0 v in t5v - ttl level input pin with 5v tolerance. input low voltage vil 0.8 v input high voltage vih 2.0 v input high leakage ilih +1 a vin = vdd input low leakage ilil -1 a vin = 0 v in ts5v - ttl level input pin with schmitt trigger, 5v tolerance. input low voltage vil 0.8 v input high voltage vih 2.0 v input high leakage ilih +1 a vin = vdd input low leakage ilil -1 a vin = 0 v od 12 -open-drain output with12 ma sink capability. output low current iol -12 ma vol = 0.4v od 12-5v -open-drain output with12 ma sink capability, 5v tolerance. output low current iol -12 ma vol = 0.4v od 24 -open-drain output with 24 ma sink capability. output low current iol -24 ma vol = 0.4v od 16-u10-5v -open-drain output with 16 ma sink capability, pull-up 10k ohms, 5v tolerance. output low current iol -16 ma vol = 0.4v o 8 - output pin with 8 ma source-sink capability. output high current ioh +6 +8 ma voh = 2.4v o 8-u47-5v - output pin with 8 ma source-sink capability, pull-up 47k ohms, 5v tolerance. output high current ioh +6 +8 ma voh = 2.4v o 12 - output pin with 12 ma source-sink capability. output high current ioh +9 +12 ma voh = 2.4v o 30 - output pin with 30 ma source-sink capability.
dec, 2010 v0.18p 116 F71808A F71808Au xxxx lab xxxxxx.x 10. ordering information part number package type production flow F71808Au 64-tqfp green package commercial, 0 c to +70 c fintek version identification: ex: for lab version the version shows on red area. ex: lab
dec, 2010 v0.18p 117 F71808A 11. package dimensions 64 tqfp feature integration technology inc. headquarters taipei office 3f-7, no 36, tai yuan st., bldg. k4, 7f, no.700, chung cheng rd., chupei city, hsinchu, taiwan 302, r.o.c. chungho city, taipei, taiwan 235, r.o.c. tel : 886-3-5600168 tel : 866-2-8227-8027 fax : 886-3-5600166 fax : 866-2-8227-8037 www: http://www.fintek.com.tw please note that all datasheet and specifications ar e subject to change without notice. all the trade marks of products and companies mentioned in this datasheet belong to their respective owne r
dec, 2010 v0.18p 118 F71808A 12. application circuits atx_5vsb 5vsb (from atx) (for device) c9 100uf c11 100uf md at ctrl0# r7 0 atx_5vsb r11 nc/0 cirrx fanctl3 r10 4.7k cirrx r25 4.7k r27 1k c10 1u io_bat d2+ copen# d1+ vref vdimm(vin3) vcore(vin1) vldt(vin2) 3vsb r5 4.7k io_bat c2 0.1u c3 0.1u copne# d3 1n4148 vbat io_bat r1 2m 3vsb copen# c4 0.1u d1 zc2800e/sot r2 10 cirrx (from atx) atx_5vsb r6 4.7k vcc3v s3# atx_pg pwok pson# rsmrst# atx_5vsb r8 4.7k r15 4.7k fanin3 cirtx cirtx r9 0 v5a vldt_en vcore_en peci ri1# dcd1# dtr1# cts1# dsr1# rts1# sin1 sout1 sus_warn_in# fanctl1 fanin1 fanctl2 fanin2 cirled strap_pwok cirtx r19 0 r20 0 q1 mosfet p d2 zc2800e/sot q2 mosfet p cirled cirled cirwb# cirwb# mc lk c8 0.1u pme# sout1 i_vsb3v 3vcc 1 lreset# 2 serirq 3 lframe# 4 lad0 5 lad1 6 lad2 7 lad3 8 pciclk 9 clkin 10 gnd 11 kbrst# 12 ga20 13 kdat/gpio10/fanin3 14 sus_ack#/mdat/gpio12 16 kclk/gpio11/ovt# 15 psout#/gpio14 32 psin#/gpio27 31 s5# 30 pcirst2# 29 pcirst1# 28 slp_sus#/gpio26/wdtrst#/rstcon# 27 erp_ctrl0# 26 i_vsb3v 25 s3_gate# 24 gpio25/ledvcc/wdtrst# 23 gpio24/ledvsb 22 dpwrok#/gpio23/wdtrst#/fanin3 21 erp_ctrl1#/gpio22/pwm 20 gpio21/fanin3/ovt# 19 gpio20/pme# 18 sus_warn#/mclk/gpio13/cirwb# 17 3vsb 48 vin1(vcore) 47 vin2(vldt) 46 sus_warn2#/vin3(vdimm) 45 copen# 44 cirrx 43 vref 42 d1+ 41 d2+ 40 agnd(d-) 39 5vsb 38 vbat 37 rsmrst# 36 pwok 35 pson# 34 s3# 33 sus_ack2#/vcore_en/gpio30 49 vldt_en/gpio31/sda 50 peci/sda/gpio32 51 gpio33/scl 52 gpio00/sda/dcd# 53 gpio01/ovt#/ri#/cirwb# 54 gpio02/cir_led/cts# 55 gpio03/cirtx/dtr# 56 gpio04/pwm/rts#/strap_pwok 57 gpio05/beep/dsr# 58 gpio06/sout/strap4e_2e 59 gpio07/cirwb#/sin 60 fanin1 61 fanctl1 62 fanin2/gpio35 63 fanctl2/gpio34 64 u1 F71808A 5va_pwok vcc3v kclk symbol pin no. c12 0.1u ga20 kbrst# kdat lreset# lframe# serirq lad1 lad0 lad3 lad2 clk_24/48m pciclk strap4e_2e led_vsb cir 59(sout1) r21 4.7k led_vcc (from atx) (for device) sus_warn_in# st2 c1 0.01u r3 1k ctrl1# v3a sus_ack# size document number rev date: sheet of F71808A 0.8 custom 19 thursday , june 24, 2010 power-on trip ctrl0# slp_sus# r14 0 v3a i_vsb3v atx_5vsb scl value d4 nc/1n4148 r12 4.7k r18 1k r24 0 description r16 0 57 r13 0 strap_pwok v3a 1 r26 0 1 0 0 c5 100uf c7 100uf cirwb# intel dsw i_3vsb r4 1k strap_pwok sus_ack# ctrl1# slp_sus# configuration register i/o port is 2e/2f. configuration register i/o port is 4e/4f.(default) pcirst1# sda pcirst2# c6 1u s4# pwok(pin 35) for amd(default) r17 0 pwsin# pwsout# r22 0 r23 0 pwok(pin 35) for intel
dec, 2010 v0.18p 119 F71808A (for device) md at mc lk kdat kclk vcc5v c14 100p r37 4.7k r38 4.7k f1 fuse l1 fb c15 0.1u c13 100p l3 fb 1 2 3 4 5 6 js1 m-din_6-r r39 4.7k l2 fb if you do not use the kbc, please pull-up these pin to 5vsb. c16 100p 1 2 3 4 5 6 js2 m-din_6-r c18 0.1u c17 100p l4 fb f2 fuse 1 2 3 j1 con3 r40 4.7k 5vsb ps2 keyboard interface ps2 mouse interface size document number rev date: sheet of uart ps/2 kbc 0.8 custom 29 thursday , june 24, 2010 ri1# cts1# dcd1# dsr1# if you do not use the uart port 1, please pull-up these pin to vcc3v. sin1 r28 4.7k r30 4.7k r29 4.7k r32 4.7k r31 4.7k vcc3v ring-in wake-up is supported by f71808. cts1# dcd1# rts1# dtr1# sout1 dsr1# sin1 1 2 d5 1n5819 r36 2.2k r35 4.7k dtrn1 dsrn1 ctsn1 gnd rtsn1 dcdn1 sinn1 soutn1 ctsn1 vcc 20 da1 16 da2 15 da3 13 ry1 19 ry2 18 ry3 17 ry4 14 ry5 12 gnd 11 +12v 1 dy1 5 dy2 6 dy3 8 ra1 2 ra2 3 ra3 4 ra4 7 ra9 9 -12v 10 u2 dcdn1 sinn1 dsrn1 dtrn1 rtsn1 r33 10k soutn1 5 9 4 8 3 7 2 6 1 p1 uart db9 r34 33 uart 1 port interface rin1 q3 npn rin1 +12v vcc5v 3vsb -12v rin1 ri1# 3vsb
dec, 2010 v0.18p 120 F71808A (for device) (for device) t rt2 thermistor 10k 1% d2+ vref d1+ vref d1+ d2+ r46 10k 1% t rt1 thermistor 10k 1% vdimm r43 1k_1% vd i mm(vi n 3) r44 4.7k_1% size document number rev date: sheet of h/w monitor 0.8 custom 39 thursday , june 24, 2010 r45 10k_1% vldt(vin2) vcore(vin1) vldt vcore *vin1 vin2 vin3 internal pull-down 320k ohm @amd mode r42 1k_1% ovt# vcc3v r41 4.7k ovt pull-up d- d- vdimm input level must > 1v voltage sensing. th er md a th er md c vsb3v 5vsb r50 4.7k q5 led_vsb led_vcc pled r48 4.7k vsb3v 5vsb q6 susled r49 4.7k r51 4.7k c20 3300p c19 3300p q4 pnp 3906 from cpu (for system) thermistor sensing circuit diode sensing circuit temperature sensing for system r47 10k 1% (for system)
dec, 2010 v0.18p 121 F71808A size document number rev date: sheet of fan control 0.8 custom 49 thursday , june 24, 2010 fanctl2 r60 4.7k fanctl3 r73 4.7k fanctl3 vcc3v vcc3v r58 4.7k r71 4.7k c26 0.1u r66 10k r63 27k q8 pnp r59 4.7k r57 4.7k r61 4.7k +12v + c23 47u 1 2 3 jp2 header 3 r65 330 q9 mosf et n 2n7002 d7 1n4148 c29 0.1u r78 10k r76 27k q10 pnp r72 4.7k r70 4.7k r74 4.7k +12v + c27 47u 1 2 3 jp4 header 3 r77 330 q12 mosf et n 2n7002 d9 1n4148 1 2 3 4 jp1 4 header vcc5v r52 10k r53 4.7k r56 10k r55 27k +12v + c21 47u d6 1n4148 c22 0.1u fanin1 (4 pin fan control) r54 100 fanctl1 pwm fan 1 speed control pwm fan 3 speed control pwm fan 2 speed control r67 10k 1 2 3 jp3 con3 r68 10k r69 3.9k d8 1n4148 dc fan control with op 2 3 2 1 8 4 + - u3a lm358 12v r64 27k r62 4.7k c24 47u q7 pmos c25 0.1u fanin2 q11 pmos r75 4.7k dc fan control with op 3 d10 1n4148 12v 1 2 3 jp5 con3 c30 0.1u c28 47u r81 10k r82 3.9k r80 10k r79 27k 5 6 7 8 4 + - u3b lm358 fan control for pwm or dc fanin2 fanin3 fanin3 fanctl2
dec, 2010 v0.18p 122 F71808A size document number rev date: sheet of digital sensor 0.8 custom 59 thursday , june 24, 2010 vcc3v vcc3v power sequence pull-up client peci_client client amdtsi intel peci r83 300 r84 300 vddio sid sic r85 100k scl vldt_en vcore_en r86 4.7k r87 4.7k peci sda (avoid pre-bios floating)
dec, 2010 v0.18p 123 F71808A choose power and capacitance by ir receiver 2 1 3 q15 npn3904 vcc3v r93 330 r94 100 c34 10nf r90 1.8k c31 0.1u r91 330 r92 12k cir_lr q14 2n7002 wide band ir receiver 1 2 q13 ltr-301 3vsb r88 0r r89 0r v3a out 1 vcc 2 gnd 3 case 4 u4 gp1ud260y k c33 0.1u cirrx c32 10u long rang ir receiver 1 2 3 j2 tx1 j ac k cirtx r95 100 tx port 3vsb r96 330 cirled 1 2 d11 led ir led size document number rev date: sheet of cir 0.8 a 69 thursday , june 24, 2010 cirrx cirtx cirrx cirtx cirled cirled cir_lr cirwb#
dec, 2010 v0.18p 124 F71808A r101 3k r103 10k 5vdual r102 0 sus_warn_in# r104 0 sus_warn# sus_warn_in# sus_warn detect mode2 sus_warn detect mode1 sus_warn# size document number rev date: sheet of intel dsw 0.8 a 79 thursday , june 24, 2010 q16 2n3904 q17 2n3904 r99 1k 5vsb r98 10k 3va r97 10k 5vdual_ctl sus_warn# 5vdual control sus_ack# sus_warn_in# slp_sus# intel dsw r100 4.7k 3va sus_ack#
dec, 2010 v0.18p 125 F71808A cpt pch sw1 wake event (dsw)erp_ctrl0# 5va (g3')erp_ctrl1# g3'_ctl dsw_ctl size document number rev date: sheet of dsw diagram 0.8 b 89 thursday , june 24, 2010 event_in# erp block ps_on# ps_in# ps_on# i_3vsb vbat 3vsb rsmrst# pme# pwrok vcc_gate 5vdual sus_warn# s5# s3# ri cir kb/ms rtc wake waek up event waek up event acpi block acpi block ldo3v d12 zc2800e/sot atxpg_in atx_pg dsw_ctl g3'_ctl 5vcc 5vsb_atx atx power supply f71869a/F71808A f71889a ps_out# 3va 3vsb 5vsb sus_warn# 5vsb rsmrst# slp_sus# sus_ack# pwrbtn# slp_s4# slp_s3# pme# dpwrok dsw block slp_sus# sus_ack# sus_warn# dpwrok dsw block en pwrok 3vldo gpio27
dec, 2010 v0.18p 126 F71808A 2010.6.22 remove sus_ack# multi-fucntion on pin19 0.7 0.6 2010.6.18 add multi-fucntion on pin23 pin57(strap_pwok) circuit pin30(s5#) connects s4#(chipset) 2010.5.14 add dsw multi-fucntion on pin19, 45, 49 size document number rev date: sheet of rev ision history 0.8 a 99 thursday , june 24, 2010 content v ersion 0.5 2010.6.24 notice r11 and d4 default is nc. 0.8

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